From fe8ec32a1c401f54e0791d8d241ef583e09257dc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 28 Dec 2013 12:10:32 +0100
Subject: [PATCH] Added new cell types to manual

---
 manual/CHAPTER_CellLib.tex  | 9 +++++++++
 passes/techmap/simplemap.cc | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 09be0870..61713e74 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -97,6 +97,12 @@ The width of the output port \B{Y}.
 
 Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators.
 
+The additional cell type {\tt \$bu0} is similar to {\tt \$pos}, but always
+extends unsigned arguments with zeros. ({\tt \$pos} extends unsigned arguments
+with {\tt x}-bits if the most significant bit is {\tt x}.) This is used
+internally to correctly implement the {\tt ==} and {\tt !=} operators for
+constant arguments.
+
 \subsection{Multiplexers}
 
 Multiplexers are generated by the Verilog HDL frontend for {\tt
@@ -147,6 +153,9 @@ Verilog & Cell Type \\
 \hline
 \lstinline[language=Verilog]; Y = A && B; & {\tt \$logic\_and} \\
 \lstinline[language=Verilog]; Y = A || B; & {\tt \$logic\_or} \\
+\hline
+\lstinline[language=Verilog]; Y = A === B; & {\tt \$eqx} \\
+\lstinline[language=Verilog]; Y = A !== B; & {\tt \$nex} \\
 \end{tabular}
 \hfil
 \begin{tabular}[t]{ll}
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 6b25eb9b..2480cf28 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -498,7 +498,7 @@ struct SimplemapPass : public Pass {
 		log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
 		log("primitives. The following internal cell types are mapped by this pass:\n");
 		log("\n");
-		log("  $not, $pos, $and, $or, $xor, $xnor\n");
+		log("  $not, $pos, $bu0, $and, $or, $xor, $xnor\n");
 		log("  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
 		log("  $logic_not, $logic_and, $logic_or, $mux\n");
 		log("  $sr, $dff, $dffsr, $adff, $dlatch\n");