 Steffen Vogel
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422ffd5c06
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Use pkg-config for linking tcl-tk
Both MacPorts and Homebrew have a pkg-config file for TCL. So lets use it.
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2017-02-10 10:06:54 -03:00 |
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Steffen Vogel
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9eca3671ab
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Dont mix Homebrew and MacPorts build options
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2017-02-10 10:04:42 -03:00 |
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Steffen Vogel
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a3f19f047c
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Remove space after backslash
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2017-02-09 19:08:21 -03:00 |
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Steffen Vogel
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94c76f85da
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Applied fixes from @joshhead (thanks for your effors!)
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2017-02-09 18:53:37 -03:00 |
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Steffen Vogel
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b8d531957d
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Added notes for compilation on OS X
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2017-02-07 11:16:56 -03:00 |
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Steffen Vogel
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7e08e37961
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Fix compilation on OS X in order to support both MacPorts and Homebrew
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2017-02-07 11:16:56 -03:00 |
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Steffen Vogel
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19f36271c2
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Allow standard tools to be overwritten in make invocation
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2017-02-07 11:09:15 -03:00 |
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Steffen Vogel
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44b47b57e3
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use Homebrew only if installed
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2017-01-31 10:06:06 -03:00 |
Clifford Wolf
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7481ba4750
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Improve opt_rmdff support for $dlatch cells
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2017-01-31 10:15:04 +01:00 |
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Clifford Wolf
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18ea65ef04
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Add "yosys-smtbmc --aig <aim_filename>:<aiw_filename>" support
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2017-01-30 11:38:43 +01:00 |
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Clifford Wolf
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fe29869ec5
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Add $ff and $_FF_ support to equiv_simple
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2017-01-30 10:50:38 +01:00 |
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Clifford Wolf
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e54c355b41
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Add "yosys-smtbmc --aig-noheader" and AIGER mem init support
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2017-01-28 15:15:02 +01:00 |
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Clifford Wolf
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45e10c1c89
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Be more conservative with merging large cells into FSMs
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2017-01-26 09:19:28 +01:00 |
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Clifford Wolf
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49b8160488
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Add warnings for quickly growing FSM table size in fsm_expand
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2017-01-26 09:05:59 +01:00 |
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Clifford Wolf
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b0a430f601
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-01-26 08:59:26 +01:00 |
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Clifford Wolf
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b54972c112
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Fix RTLIL::Memory::start_offset initialization
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2017-01-25 17:00:59 +01:00 |
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Clifford Wolf
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fea528280b
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Add "enum" and "typedef" lexer support
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2017-01-17 17:33:52 +01:00 |
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Clifford Wolf
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87fe8ab3f2
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Merge pull request #293 from thoughtpolice/minor-cleanup
Delete some dead code in the Hierarchy pass
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2017-01-16 10:25:25 +01:00 |
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Austin Seipp
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6781543244
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passes/hierarchy: delete some dead code
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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2017-01-15 16:39:12 -06:00 |
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Clifford Wolf
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78f65f89ff
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Fix bug in AstNode::mem2reg_as_needed_pass2()
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2017-01-15 13:52:50 +01:00 |
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Clifford Wolf
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b7cfb7dbd2
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Fix $initstate handling bug in yosys-smtbmc
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2017-01-11 14:14:12 +01:00 |
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Clifford Wolf
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8953a55cd8
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Update ABC to hg id f8cadfe3861f
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2017-01-11 10:56:27 +01:00 |
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Clifford Wolf
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8012de40b9
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Updated ABC to hg id 38b26a543f1d
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2017-01-08 11:57:52 +01:00 |
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Clifford Wolf
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2d32c6c4f6
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Fixed handling of local memories in functions
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2017-01-05 13:19:03 +01:00 |
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Clifford Wolf
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0cac95ea94
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Added "check -initdrv"
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2017-01-04 18:12:41 +01:00 |
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Clifford Wolf
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81a9ee2360
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Added handling of local memories and error for local decls in unnamed blocks
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2017-01-04 16:03:04 +01:00 |
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Clifford Wolf
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b9ad91b93e
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Implicitly set "yosys-smtbmc --noprogress" on windows
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2017-01-04 15:23:48 +01:00 |
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Clifford Wolf
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080004b19a
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Fixed typo in tests/simple/arraycells.v
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2017-01-04 12:39:01 +01:00 |
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Clifford Wolf
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ed812ea39c
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Fixed "yosys-smtbmc --noprogress"
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2017-01-04 12:03:04 +01:00 |
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Clifford Wolf
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dfb461fe52
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Added Verilog $rtoi and $itor support
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2017-01-03 17:40:58 +01:00 |
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Clifford Wolf
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81bb952e5d
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Handle "always 1" like "always -1" in .smtc files
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2017-01-02 20:08:03 +01:00 |
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Clifford Wolf
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f0df7dd796
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Added cell port resizing to hierarchy pass
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2017-01-01 23:03:44 +01:00 |
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Clifford Wolf
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a7fb64efe6
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Updated ABC to hg id 55cd83f432c0
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2016-12-31 21:52:27 +01:00 |
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Clifford Wolf
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6b2c23c721
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Bugfix in RTLIL::SigSpec::remove2()
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2016-12-31 16:14:42 +01:00 |
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Clifford Wolf
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7da7a6d1df
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Updated ABC to hg id 8c6a635f7a20
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2016-12-29 12:20:35 +01:00 |
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Clifford Wolf
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2198948398
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Improved write_json help message
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2016-12-29 12:13:29 +01:00 |
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Clifford Wolf
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4f5efc3416
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Updated ABC to hg id f591c081d5e7
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2016-12-26 17:52:38 +01:00 |
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Clifford Wolf
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4cf3170194
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Merge pull request #284 from azonenberg/master
greenpak4: Support for many new cell types
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2016-12-24 14:28:39 +01:00 |
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Andrew Zonenberg
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5ffede5c0e
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Merge pull request #1 from azonenberg-hk/master
Pull changes from HK trip
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2016-12-23 12:32:55 -08:00 |
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Andrew Zonenberg
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9f69a70d74
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Merge https://github.com/cliffordwolf/yosys
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2016-12-23 05:10:37 -08:00 |
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Clifford Wolf
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33a22f8768
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Simplified log_spacer() code
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2016-12-23 02:06:46 +01:00 |
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Clifford Wolf
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a0dff87a57
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Added "yosys -W regex"
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2016-12-22 23:41:44 +01:00 |
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Clifford Wolf
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f144adec58
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Added AIGER back-end to automatic back-end detection
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2016-12-21 10:16:47 +01:00 |
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Clifford Wolf
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f31e6a7174
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Updated ABC to hg rev a4872e22c646
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2016-12-21 10:16:10 +01:00 |
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Clifford Wolf
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3d0e51f813
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Updated ABC to hg rev 8bab2eedbba4
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2016-12-21 09:13:20 +01:00 |
|
Andrew Zonenberg
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ada98844b9
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greenpak4: Added INT pin to GP_SPI
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2016-12-21 11:35:29 +08:00 |
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Andrew Zonenberg
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6b526e9382
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greenpak4: removed unused MISO pin from GP_SPI
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2016-12-21 11:33:32 +08:00 |
|
Andrew Zonenberg
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638f3e3b12
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greenpak4: Removed SPI_BUFFER parameter
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2016-12-20 13:07:49 +08:00 |
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Andrew Zonenberg
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073e8df9f1
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greenpak4: replaced MOSI/MISO with single one-way SDAT pin
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2016-12-20 12:34:56 +08:00 |
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Andrew Zonenberg
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d4a05b499e
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greenpak4: Changed port names on GP_SPI for clarity
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2016-12-20 10:30:38 +08:00 |