Clifford Wolf
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06d35ea942
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Improved TCL_VERSION detection so it does not read .tclshrc
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2016-04-29 10:26:22 +02:00 |
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Clifford Wolf
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e01464e2ac
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Added "qwp -v"
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2016-04-28 23:17:30 +02:00 |
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Clifford Wolf
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0d2923cccd
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Connections between inputs and inouts are driven by the input
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2016-04-26 19:49:05 +02:00 |
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Clifford Wolf
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958fb29c76
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Fixed test_autotb for modules with many cell ports
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2016-04-25 16:37:11 +02:00 |
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Clifford Wolf
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93e107e455
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Fixed proc_mux performance bug
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2016-04-25 10:43:04 +02:00 |
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Clifford Wolf
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d086224a39
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Merge pull request #150 from azonenberg/master
GreenPak analog comparator support
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2016-04-25 10:33:18 +02:00 |
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Andrew Zonenberg
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d57c85111f
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Merge https://github.com/cliffordwolf/yosys
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2016-04-24 22:11:56 -07:00 |
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Andrew Zonenberg
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349d717202
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Removed VIN_BUF_EN
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2016-04-24 17:01:21 -07:00 |
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Clifford Wolf
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b1d6f05fa2
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Fixed performance bug in proc_dlatch
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2016-04-24 19:29:56 +02:00 |
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Clifford Wolf
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9aa4b3309c
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Added "yosys -D ALL"
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2016-04-24 17:12:34 +02:00 |
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Andrew Zonenberg
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6e215f374d
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Renamed VOUT to OUT on GP_ACMP cell
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2016-04-23 22:53:49 -07:00 |
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Andrew Zonenberg
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512486dcf3
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Added GP_ACMP cell
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2016-04-23 22:33:36 -07:00 |
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Clifford Wolf
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09ffebb995
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Added "prep -flatten" and "synth -flatten"
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2016-04-24 00:48:33 +02:00 |
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Clifford Wolf
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77aa2031e7
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Converted "prep" to ScriptPass
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2016-04-24 00:48:06 +02:00 |
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Clifford Wolf
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096c25d29d
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Improvements in greenpak4 shreg mapping
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2016-04-23 23:10:13 +02:00 |
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Clifford Wolf
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c9c5192cd6
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Run clean after splitnets in synth_greenpak4
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2016-04-23 23:09:45 +02:00 |
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Andrew Zonenberg
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7f16784f3c
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Merge https://github.com/cliffordwolf/yosys
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2016-04-23 12:22:08 -07:00 |
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Clifford Wolf
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e13c66122e
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Added "shregmap -zinit" for greenpak4 tech
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2016-04-23 20:20:21 +02:00 |
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Andrew Zonenberg
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421b0d715c
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Merge https://github.com/cliffordwolf/yosys
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2016-04-23 10:18:15 -07:00 |
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Clifford Wolf
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34195f281f
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Merge https://github.com/azonenberg/yosys
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2016-04-23 10:33:32 +02:00 |
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Clifford Wolf
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f85cfa5666
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Added "shregmap" to synth_greenpak4
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2016-04-23 10:31:19 +02:00 |
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Clifford Wolf
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a24021ea20
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Converted synth_greenpak4 to ScriptPass
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2016-04-23 10:27:33 +02:00 |
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Andrew Zonenberg
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2849fd486e
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Fixed typo in help text
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2016-04-22 23:01:39 -07:00 |
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Andrew Zonenberg
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0cbe70eaa4
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Fixed typo
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2016-04-22 19:08:19 -07:00 |
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Andrew Zonenberg
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ab11f2aa70
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Merge https://github.com/cliffordwolf/yosys
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2016-04-22 19:07:55 -07:00 |
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Clifford Wolf
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7311be4028
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Added "shregmap -tech greenpak4"
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2016-04-22 19:42:08 +02:00 |
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Clifford Wolf
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779e2cc819
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Added support for "active high" and "active low" latches in BLIF front-end
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2016-04-22 18:02:55 +02:00 |
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Clifford Wolf
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60ac1bd178
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Added support for "active high" and "active low" latches in BLIF back-end
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2016-04-22 18:00:46 +02:00 |
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Clifford Wolf
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965b0d59b5
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More flexible handling of initialization values
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2016-04-22 12:13:06 +02:00 |
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Clifford Wolf
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0bc95f1e04
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Added "yosys -D" feature
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2016-04-21 23:28:37 +02:00 |
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Clifford Wolf
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1565d1af69
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Fixed performance bug in "share" pass
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2016-04-21 19:47:25 +02:00 |
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Clifford Wolf
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5a09fa4553
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Fixed handling of parameters and const functions in casex/casez pattern
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2016-04-21 15:31:54 +02:00 |
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Clifford Wolf
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f38ca3e18f
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Improvements in opt_expr
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2016-04-21 14:23:04 +02:00 |
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Clifford Wolf
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1761d08dd2
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Bugfix and improvements in memory_share
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2016-04-21 14:22:58 +02:00 |
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Andrew Zonenberg
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d90c1e9522
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Added GP_VREF cell
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2016-04-20 20:48:19 -07:00 |
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Clifford Wolf
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bf64974d43
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Merge pull request #149 from azonenberg/master
GP_RCOSC and GP_SHREG cells plus some cleanup
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2016-04-19 10:37:04 +02:00 |
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Andrew Zonenberg
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8c9ac5db7b
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Merge https://github.com/cliffordwolf/yosys
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2016-04-18 19:22:52 -07:00 |
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Clifford Wolf
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f1fa757d0e
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Added "shregmap -params"
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2016-04-18 11:58:21 +02:00 |
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Clifford Wolf
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525651c8f6
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Added "shregmap -zinit" and "shregmap -init"
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2016-04-18 11:44:10 +02:00 |
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Andrew Zonenberg
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b2c36f6136
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Merge https://github.com/cliffordwolf/yosys
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2016-04-17 08:15:34 -07:00 |
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Clifford Wolf
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ce7c980ec7
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Improvements in "shregmap"
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2016-04-17 15:37:22 +02:00 |
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Andrew Zonenberg
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be570712d8
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Merge https://github.com/cliffordwolf/yosys
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2016-04-16 15:14:32 -07:00 |
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Clifford Wolf
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de647a390c
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Added "shregmap" pass
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2016-04-16 23:20:49 +02:00 |
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Clifford Wolf
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fbdb8e7b3e
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Fixed copy&paste error in log message in lut2mux
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2016-04-16 23:20:34 +02:00 |
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Clifford Wolf
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a07f893a5f
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Minor hashlib bugfix
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2016-04-16 23:20:11 +02:00 |
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Andrew Zonenberg
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d0aaf8d262
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Added GP_SHREG cell
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2016-04-13 23:13:51 -07:00 |
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Andrew Zonenberg
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cdefa60367
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Refactoring: alphabetized cells_sim
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2016-04-13 23:13:39 -07:00 |
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Andrew Zonenberg
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f1679936fe
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Fixed missing semicolon
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2016-04-09 01:18:02 -07:00 |
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Andrew Zonenberg
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c1b8d3b580
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Merge https://github.com/cliffordwolf/yosys
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2016-04-09 01:17:24 -07:00 |
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Andrew Zonenberg
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58d8715681
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Added GP_RCOSC cell
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2016-04-09 01:17:13 -07:00 |
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