Clifford Wolf
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0bd8fafbd2
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Added RTLIL::Design::modules()
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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d088854b47
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Added conversion from ObjRange to std::vector and std::set
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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1c8fdaeef8
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Added RTLIL::ObjIterator and RTLIL::ObjRange
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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ddc5b41848
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Using std::move() in SigSpec move constructor
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2014-07-27 09:20:59 +02:00 |
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Clifford Wolf
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7f3dc86ecd
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Added RTLIL::SigSpec move constructor and move assignment operator
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2014-07-27 02:11:57 +02:00 |
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Clifford Wolf
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c91570bde3
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Mostly cosmetic changes to rtlil.h
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2014-07-27 02:00:04 +02:00 |
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Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
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Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
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Clifford Wolf
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d68c993ed2
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Changed more code to the new RTLIL::Wire constructors
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2014-07-26 21:30:38 +02:00 |
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Clifford Wolf
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946ddff9ce
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Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26 20:12:50 +02:00 |
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Clifford Wolf
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97a59851a6
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Added RTLIL::Cell::has(portname)
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2014-07-26 16:11:28 +02:00 |
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Clifford Wolf
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cd6574ecf6
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Added some missing "const" in rtlil.h
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2014-07-26 15:58:22 +02:00 |
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Clifford Wolf
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7ac9dc7f6e
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Added RTLIL::Module::connections()
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2014-07-26 15:58:21 +02:00 |
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Clifford Wolf
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b03aec6e32
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Added RTLIL::Module::connect(const RTLIL::SigSig&)
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2014-07-26 14:31:47 +02:00 |
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Clifford Wolf
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3719281ed4
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Automatically pack SigSpec on copy/assign
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2014-07-26 13:59:30 +02:00 |
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Clifford Wolf
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e75e495c2b
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Added new RTLIL::Cell port access methods
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2014-07-26 12:22:58 +02:00 |
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Clifford Wolf
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cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
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Clifford Wolf
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4755e14e7b
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Added copy-constructor-like module->addCell(name, other) method
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2014-07-26 00:38:44 +02:00 |
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Clifford Wolf
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2bec47a404
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Use only module->addCell() and module->remove() to create and delete cells
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2014-07-25 17:56:19 +02:00 |
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Clifford Wolf
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c762050e7f
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Added RTLIL::SigSpec is_chunk()/as_chunk() API
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2014-07-25 14:23:10 +02:00 |
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Clifford Wolf
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6aa792c864
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Replaced more old SigChunk programming patterns
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2014-07-24 23:10:58 +02:00 |
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Clifford Wolf
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22ede43b3f
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Small changes regarding cover() and check() in SigSpec
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2014-07-24 04:46:36 +02:00 |
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Clifford Wolf
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82fa356037
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Added hashing to RTLIL::SigSpec relational and equal operators
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2014-07-23 23:58:03 +02:00 |
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Clifford Wolf
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2a41afb7b2
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Added RTLIL::SigSpec::repeat()
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2014-07-23 21:34:14 +02:00 |
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Clifford Wolf
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c094c53de8
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Removed RTLIL::SigSpec::optimize()
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2014-07-23 20:32:28 +02:00 |
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Clifford Wolf
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a62c21c9c6
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Removed RTLIL::SigSpec::expand() method
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2014-07-23 19:34:51 +02:00 |
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Clifford Wolf
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4e802eb7f6
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Fixed all users of SigSpec::chunks_rw() and removed it
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2014-07-23 15:36:09 +02:00 |
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Clifford Wolf
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85db102e13
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Replaced RTLIL::SigSpec::operator!=() with inline version
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2014-07-23 15:35:09 +02:00 |
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Clifford Wolf
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ec923652e2
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
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2014-07-23 09:52:55 +02:00 |
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Clifford Wolf
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260c19ec5a
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
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2014-07-23 09:34:47 +02:00 |
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Clifford Wolf
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c61467a32c
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Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)
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2014-07-23 08:59:54 +02:00 |
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Clifford Wolf
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9e94f41b89
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SigSpec refactoring: Added RTLIL::SigSpecIterator
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2014-07-22 23:49:26 +02:00 |
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Clifford Wolf
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f80da7b41d
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SigSpec refactoring: added RTLIL::SigSpec::operator[]
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2014-07-22 22:54:03 +02:00 |
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Clifford Wolf
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a97be0828a
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Removed RTLIL::SigChunk::compare()
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2014-07-22 21:40:52 +02:00 |
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Clifford Wolf
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08e1e25169
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SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api
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2014-07-22 21:33:52 +02:00 |
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Clifford Wolf
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28b3fd05fa
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
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2014-07-22 20:58:44 +02:00 |
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Clifford Wolf
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7bffde6abd
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SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
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2014-07-22 20:39:38 +02:00 |
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Clifford Wolf
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4b4048bc5f
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SigSpec refactoring: using the accessor functions everywhere
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2014-07-22 20:39:37 +02:00 |
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Clifford Wolf
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16e5ae0b92
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SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions
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2014-07-22 20:39:37 +02:00 |
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Clifford Wolf
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a233762a81
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SigSpec refactoring: renamed chunks and width to __chunks and __width
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2014-07-22 20:39:37 +02:00 |
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Clifford Wolf
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361e0d62ff
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Replaced depricated NEW_WIRE macro with module->addWire() calls
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2014-07-21 12:42:02 +02:00 |
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Clifford Wolf
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1d88f1cf9f
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Removed deprecated module->new_wire()
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2014-07-21 12:35:06 +02:00 |
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Clifford Wolf
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54b0f2e659
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Added module->remove(), module->addWire(), module->addCell(), cell->check()
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2014-07-21 12:02:55 +02:00 |
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Clifford Wolf
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e57db5e9b2
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Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
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2014-07-20 11:01:04 +02:00 |
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Clifford Wolf
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efa7884026
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Added SIZE() macro
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2014-07-20 10:36:14 +02:00 |
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Clifford Wolf
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a721f7d768
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Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>
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2014-07-18 11:36:34 +02:00 |
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Clifford Wolf
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2d69c309f9
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Added function-like cell creation helpers
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2014-07-18 10:27:06 +02:00 |
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Clifford Wolf
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d4a1b0af5b
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Added support for dlatchsr cells
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2014-03-31 14:14:40 +02:00 |
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Clifford Wolf
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b7c71d92f6
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Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
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2014-03-15 14:35:29 +01:00 |
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