Commit graph

8 commits

Author SHA1 Message Date
Clifford Wolf
f1a2fd966f Now only use value from "initial" when no matching "always" block is found 2013-03-31 11:51:12 +02:00
Clifford Wolf
161565be10 Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS) 2013-03-31 11:19:11 +02:00
Clifford Wolf
7bfc7b61a8 Implemented proper handling of stub placeholder modules 2013-03-28 09:20:10 +01:00
Clifford Wolf
227520f94d Added nosync attribute and some async reset related fixes 2013-03-25 17:13:14 +01:00
Clifford Wolf
df9753d398 Added mem2reg option to verilog frontend 2013-03-24 11:13:32 +01:00
Clifford Wolf
bb3357c027 Improved mem2reg handling in ast simplifier 2013-03-24 09:27:01 +01:00
Clifford Wolf
4f0c2862a0 Added support for verilog genblock[index].member syntax 2013-02-26 13:18:22 +01:00
Clifford Wolf
7764d0ba1d initial import 2013-01-05 11:13:26 +01:00