Clifford Wolf
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b2544cfcf7
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Fixed segfault in AstNode::asReal
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2015-09-25 12:38:01 +02:00 |
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Clifford Wolf
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1b8cb9940e
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Fixed AstNode::mkconst_bits() segfault on zero-sized constant
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2015-09-24 11:21:20 +02:00 |
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Larry Doolittle
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6c00704a5e
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Another block of spelling fixes
Smaller this time
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2015-08-14 23:27:05 +02:00 |
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Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
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Clifford Wolf
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1f1deda888
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Added non-std verilog assume() statement
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2015-02-26 18:47:39 +01:00 |
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Clifford Wolf
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7f1a1759d7
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Added "read_verilog -nomeminit" and "nomeminit" attribute
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2015-02-14 11:21:12 +01:00 |
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Clifford Wolf
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a8e9d37c14
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Creating $meminit cells in verilog front-end
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2015-02-14 10:49:30 +01:00 |
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Clifford Wolf
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0bb6b24c11
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Added global yosys_celltypes
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2014-12-29 14:30:33 +01:00 |
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Clifford Wolf
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90bc71dd90
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dict/pool changes in ast
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2014-12-29 03:11:50 +01:00 |
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Clifford Wolf
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137f35373f
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Changed more code to dict<> and pool<>
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2014-12-28 19:24:24 +01:00 |
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Clifford Wolf
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a6c96b986b
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Added Yosys::{dict,nodict,vector} container types
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2014-12-26 10:53:21 +01:00 |
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Clifford Wolf
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26cbe4a4e5
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Fixed constant "cond ? string1 : string2" with strings of different size
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2014-10-25 18:23:53 +02:00 |
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Clifford Wolf
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750c615e7f
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minor indenting corrections
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2014-10-19 18:42:03 +02:00 |
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Parviz Palangpour
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de8adb8ec5
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Builds on Mac 10.9.2 with LLVM 3.5.
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2014-10-19 11:14:43 -05:00 |
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Clifford Wolf
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35fbc0b35f
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Do not the 'z' modifier in format string (another win32 fix)
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2014-10-11 11:42:08 +02:00 |
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Clifford Wolf
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98442e019d
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Added emscripten (emcc) support to build system and some build fixes
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2014-08-22 16:20:22 +02:00 |
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Clifford Wolf
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085c8e873d
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Added AstNode::asInt()
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2014-08-21 17:11:51 +02:00 |
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Clifford Wolf
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7bfc4ae120
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Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
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2014-08-21 12:43:51 +02:00 |
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Clifford Wolf
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38addd4c67
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Added support for global tasks and functions
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2014-08-21 12:42:28 +02:00 |
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Clifford Wolf
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acb435b6cf
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Added const folding of AST_CASE to AST simplifier
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2014-08-18 00:02:30 +02:00 |
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Clifford Wolf
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d491fd8c19
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Use stackmap<> in AST ProcessGenerator
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2014-08-17 00:57:24 +02:00 |
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Clifford Wolf
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c7afbd9d8e
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Fixed bug in "read_verilog -ignore_redef"
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2014-08-15 01:53:22 +02:00 |
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Clifford Wolf
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c83b990458
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Changed the AST genWidthRTLIL subst interface to use a std::map
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2014-08-14 23:02:07 +02:00 |
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Clifford Wolf
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1bf7a18fec
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Added module->ports
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2014-08-14 16:22:52 +02:00 |
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Clifford Wolf
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d259abbda2
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Added AST_MULTIRANGE (arrays with more than 1 dimension)
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2014-08-06 15:52:54 +02:00 |
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Clifford Wolf
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14412e6c95
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Preparations for RTLIL::IdString redesign: cleanup of existing code
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2014-08-02 00:45:25 +02:00 |
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Clifford Wolf
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bd74ed7da4
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Replaced sha1 implementation
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2014-08-01 19:01:10 +02:00 |
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Clifford Wolf
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e6d33513a5
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Added module->design and cell->module, wire->module pointers
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2014-07-31 14:11:39 +02:00 |
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Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
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Clifford Wolf
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27a872d1e7
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
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Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
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Clifford Wolf
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c4bdba78cb
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Added proper Design->addModule interface
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2014-07-27 21:12:09 +02:00 |
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Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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82bbd2f077
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Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
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2014-06-16 15:05:37 +02:00 |
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Clifford Wolf
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4d1df128fa
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Improved AstNode::realAsConst for large numbers
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2014-06-15 09:27:09 +02:00 |
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Clifford Wolf
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48dc6ab98d
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Improved AstNode::asReal for large integers
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2014-06-15 08:38:31 +02:00 |
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Clifford Wolf
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149fe83a8d
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improved (fixed) conversion of real values to bit vectors
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2014-06-14 21:00:51 +02:00 |
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Clifford Wolf
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9bd7d5c468
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Added handling of real-valued parameters/localparams
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2014-06-14 12:00:47 +02:00 |
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Clifford Wolf
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442a8e2875
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Implemented basic real arithmetic
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2014-06-14 08:51:22 +02:00 |
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Clifford Wolf
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7ef0da32cd
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Added Verilog lexer and parser support for real values
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2014-06-13 11:29:23 +02:00 |
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Clifford Wolf
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e275e8eef9
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Add support for cell arrays
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2014-06-07 11:48:50 +02:00 |
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Clifford Wolf
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b5cd7a0179
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added while and repeat support to verilog parser
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2014-06-06 17:40:04 +02:00 |
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Clifford Wolf
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09805ee9ec
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Include id2ast pointers when dumping AST
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2014-03-05 19:56:31 +01:00 |
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Clifford Wolf
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4bd25edcd4
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Cleanups in handling of read_verilog -defer and -icells
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2014-02-20 19:12:32 +01:00 |
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Clifford Wolf
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02e6f2c5be
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Added Verilog support for "`default_nettype none"
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2014-02-17 14:28:52 +01:00 |
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Clifford Wolf
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e8af3def7f
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Added support for FOR loops in function calls in parameters
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2014-02-14 20:33:22 +01:00 |
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Clifford Wolf
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534c1a5dd0
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Created basic support for function calls in parameter values
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2014-02-14 19:56:44 +01:00 |
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Clifford Wolf
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cd9e8741a7
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Implemented read_verilog -defer
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2014-02-13 13:59:13 +01:00 |
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Clifford Wolf
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d06258f74f
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Added constant size expression support of sized constants
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2014-02-01 13:50:23 +01:00 |
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Clifford Wolf
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375c4dddc1
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Added read_verilog -icells option
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2014-01-29 00:59:28 +01:00 |
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