Clifford Wolf
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2a9ad48eb6
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Added ENABLE_NDEBUG makefile options
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2015-01-24 12:16:46 +01:00 |
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Clifford Wolf
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df9d096a7d
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Ignoring more system task and functions
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2015-01-15 13:08:19 +01:00 |
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Clifford Wolf
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a588a4a5c9
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Fixed handling of "input foo; reg [0:0] foo;"
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2015-01-15 12:53:12 +01:00 |
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Clifford Wolf
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8e8e791fb5
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Consolidate "Blocking assignment to memory.." msgs for the same line
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2015-01-15 12:41:52 +01:00 |
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Fabio Utzig
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fff6f00b3c
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Enable bison to be customized
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2015-01-08 09:56:20 -02:00 |
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Clifford Wolf
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1bd67d792e
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Define YOSYS and SYNTHESIS in preproc
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2015-01-02 17:11:54 +01:00 |
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Clifford Wolf
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eefe78be09
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Fixed memory->start_offset handling
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2015-01-01 12:56:01 +01:00 |
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Clifford Wolf
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0bb6b24c11
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Added global yosys_celltypes
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2014-12-29 14:30:33 +01:00 |
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Clifford Wolf
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90bc71dd90
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dict/pool changes in ast
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2014-12-29 03:11:50 +01:00 |
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Clifford Wolf
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137f35373f
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Changed more code to dict<> and pool<>
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2014-12-28 19:24:24 +01:00 |
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Clifford Wolf
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7751c491fb
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Improved some warning messages
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2014-12-27 03:40:27 +01:00 |
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Clifford Wolf
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12ca6538a4
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Fixed mem2reg warning message
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2014-12-27 03:26:30 +01:00 |
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Clifford Wolf
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a6c96b986b
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Added Yosys::{dict,nodict,vector} container types
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2014-12-26 10:53:21 +01:00 |
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Clifford Wolf
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edb3c9d0c4
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Renamed extend() to extend_xx(), changed most users to extend_u0()
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2014-12-24 09:51:17 +01:00 |
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Clifford Wolf
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1282a113da
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Fixed supply0/supply1 with many wires
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2014-12-11 13:56:20 +01:00 |
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Clifford Wolf
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76c83283c4
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Fixed minor bug in parsing delays
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2014-11-24 14:48:07 +01:00 |
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Clifford Wolf
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56c7d1e266
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Fixed two minor bugs in constant parsing
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2014-11-24 14:39:24 +01:00 |
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Clifford Wolf
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87333f3ae2
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Added warning for use of 'z' constants in HDL
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2014-11-14 19:59:50 +01:00 |
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Clifford Wolf
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4e5350b409
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Fixed parsing of nested verilog concatenation and replicate
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2014-11-12 19:10:35 +01:00 |
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Clifford Wolf
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fe829bdbdc
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Added log_warning() API
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2014-11-09 10:44:23 +01:00 |
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Clifford Wolf
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acf010d30d
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Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions
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2014-11-08 11:38:44 +01:00 |
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Clifford Wolf
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a21481b338
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Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
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2014-10-30 14:01:02 +01:00 |
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Clifford Wolf
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37aa2e02db
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AST simplifier: optimize constant AST_CASE nodes before recursively descending
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2014-10-29 08:29:51 +01:00 |
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Clifford Wolf
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f9c096eeda
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Added support for task and function args in parentheses
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2014-10-27 13:21:57 +01:00 |
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Clifford Wolf
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c4a2b3c1e9
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Improvements in $readmem[bh] implementation
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2014-10-26 23:29:36 +01:00 |
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Clifford Wolf
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70b2efdb05
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Added support for $readmemh/$readmemb
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2014-10-26 20:33:10 +01:00 |
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Clifford Wolf
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26cbe4a4e5
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Fixed constant "cond ? string1 : string2" with strings of different size
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2014-10-25 18:23:53 +02:00 |
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Clifford Wolf
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c5eb5e56b8
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Re-introduced Yosys::readsome() helper function
(f.read() + f.gcount() made problems with lines > 16kB)
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2014-10-23 10:58:36 +02:00 |
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Clifford Wolf
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750c615e7f
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minor indenting corrections
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2014-10-19 18:42:03 +02:00 |
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Parviz Palangpour
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de8adb8ec5
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Builds on Mac 10.9.2 with LLVM 3.5.
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2014-10-19 11:14:43 -05:00 |
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Clifford Wolf
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84ffe04075
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Fixed various VS warnings
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2014-10-18 15:20:38 +02:00 |
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William Speirs
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31267a1ae8
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Header changes so it will compile on VS
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2014-10-17 11:41:36 +02:00 |
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William Speirs
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fda52f05f2
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Wrapped math in int constructor
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2014-10-17 11:28:14 +02:00 |
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Clifford Wolf
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3838856a9e
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Print "SystemVerilog" in "read_verilog -sv" log messages
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2014-10-16 10:31:54 +02:00 |
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Clifford Wolf
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6b05a9e807
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Fixed handling of invalid array access in mem2reg code
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2014-10-16 00:44:23 +02:00 |
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Clifford Wolf
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f65e1c309f
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Updated .gitignore file for ilang and verilog frontends
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2014-10-15 01:14:38 +02:00 |
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Clifford Wolf
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c3e9922b5d
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Replaced readsome() with read() and gcount()
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2014-10-15 01:12:53 +02:00 |
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William Speirs
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fad0b0c506
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Updated lexers & parsers to include prefixes
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2014-10-15 00:48:19 +02:00 |
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Clifford Wolf
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0b9282a779
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Added make_temp_{file,dir}() and remove_directory() APIs
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2014-10-12 12:11:57 +02:00 |
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Clifford Wolf
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b1596bc0e7
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Added run_command() api to replace system() and popen()
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2014-10-12 10:57:15 +02:00 |
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Clifford Wolf
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35fbc0b35f
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Do not the 'z' modifier in format string (another win32 fix)
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2014-10-11 11:42:08 +02:00 |
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Clifford Wolf
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8263f6a74a
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Fixed win32 troubles with f.readsome()
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2014-10-11 11:36:22 +02:00 |
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Clifford Wolf
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0a651f112f
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Disabled vhdl2verilog command for win32 builds
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2014-10-11 10:46:19 +02:00 |
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Clifford Wolf
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bbd808072b
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Added format __attribute__ to stringf()
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2014-10-10 17:22:08 +02:00 |
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Clifford Wolf
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4569a747f8
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Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
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Clifford Wolf
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f9a307a50b
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namespace Yosys
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2014-09-27 16:17:53 +02:00 |
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Clifford Wolf
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48b00dccea
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Another $clog2 bugfix
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2014-09-08 12:25:23 +02:00 |
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Clifford Wolf
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680eaaac41
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Fixed $clog2 (off by one error)
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2014-09-06 19:31:04 +02:00 |
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Clifford Wolf
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deff416ea7
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Fixed assignment of out-of bounds array element
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2014-09-06 17:58:27 +02:00 |
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Ruben Undheim
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79cbf9067c
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Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
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