Clifford Wolf
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2442eb3832
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Fixed monitor notifications for removed cell
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2014-09-14 17:04:39 +02:00 |
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Clifford Wolf
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7815f81c32
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Added "synth" command
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2014-09-14 16:09:06 +02:00 |
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Clifford Wolf
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7e156a5419
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Fixed techmap_wrap for techmap_celltype
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2014-09-14 15:34:36 +02:00 |
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Clifford Wolf
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923bbbeaf0
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Using alumacc in techmap.v
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2014-09-14 14:50:15 +02:00 |
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Clifford Wolf
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014bb34e0e
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Various fixes/cleanups in alumacc and maccmap
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2014-09-14 14:49:53 +02:00 |
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Clifford Wolf
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124e759280
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Added techmap_wrap attribute
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2014-09-14 14:49:26 +02:00 |
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Clifford Wolf
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b34ca15185
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alumacc fix for $pos cells
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2014-09-14 14:00:14 +02:00 |
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Clifford Wolf
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0df1d9ad72
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Extract $alu cells in alumacc
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2014-09-14 13:23:44 +02:00 |
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Clifford Wolf
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7b16c63101
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Merge $macc cells in alumacc pass
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2014-09-14 11:21:37 +02:00 |
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Clifford Wolf
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0b72f0acb1
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Basic $macc extract in alumacc
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2014-09-14 10:45:28 +02:00 |
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Clifford Wolf
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ff157fb74f
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alumacc skeleton
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2014-09-14 10:02:00 +02:00 |
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Clifford Wolf
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aab0e3bf70
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Cleanup in wreduce
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2014-09-14 10:01:30 +02:00 |
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Clifford Wolf
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3ae96f85a5
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Using pkg-config to find libffi
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2014-09-13 17:28:15 +02:00 |
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Clifford Wolf
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44b5bd4b63
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Fixed simlib $macc model for xilinx xsim
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2014-09-08 17:09:39 +02:00 |
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Clifford Wolf
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fcb46138ce
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Simplified $fa undef model
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2014-09-08 16:59:39 +02:00 |
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Clifford Wolf
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6dc07eb1f2
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Fixes and cleanups for blackbox.v
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2014-09-08 13:31:04 +02:00 |
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Clifford Wolf
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af0c8873bb
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Added $lcu cell type
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2014-09-08 13:31:04 +02:00 |
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Clifford Wolf
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48b00dccea
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Another $clog2 bugfix
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2014-09-08 12:25:23 +02:00 |
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Clifford Wolf
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d46bac3305
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Added "$fa" cell type
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2014-09-08 12:15:39 +02:00 |
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Clifford Wolf
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1a88e47396
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Trim msb/lsb zero bits from full adder in maccmap
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2014-09-08 11:21:58 +02:00 |
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Clifford Wolf
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6747a7047e
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Added "test_cell -const"
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2014-09-08 11:12:39 +02:00 |
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Clifford Wolf
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dd887cc025
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Using maccmap for $macc and $mul techmap
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2014-09-07 18:24:08 +02:00 |
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Clifford Wolf
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c50b841b29
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Added 'techmap_maccmap' techmap attribute
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2014-09-07 18:23:37 +02:00 |
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Clifford Wolf
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015dcdc84c
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Added "maccmap" command
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2014-09-07 18:23:04 +02:00 |
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Clifford Wolf
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15b3c54fea
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Added "test_cell -nosat"
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2014-09-07 17:05:41 +02:00 |
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Clifford Wolf
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9329a76818
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Various bug fixes (related to $macc model testing)
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2014-09-06 20:30:46 +02:00 |
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Clifford Wolf
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98e6463ca7
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Added $macc eval model
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2014-09-06 19:44:28 +02:00 |
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Clifford Wolf
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fa64942018
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Added $macc SAT model
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2014-09-06 19:44:11 +02:00 |
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Clifford Wolf
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680eaaac41
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Fixed $clog2 (off by one error)
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2014-09-06 19:31:04 +02:00 |
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Clifford Wolf
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bff4706b62
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Added $macc simlib model (also use as techmap rule for now)
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2014-09-06 17:59:12 +02:00 |
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Clifford Wolf
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deff416ea7
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Fixed assignment of out-of bounds array element
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2014-09-06 17:58:27 +02:00 |
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Clifford Wolf
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b847ec8a0b
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Added $macc cell type
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2014-09-06 15:47:46 +02:00 |
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Clifford Wolf
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76f8128123
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Fixed autotest for non-basename arguments
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2014-09-06 12:10:57 +02:00 |
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Clifford Wolf
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34af6a1303
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-09-06 11:46:44 +02:00 |
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Clifford Wolf
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e1743b3bac
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Added "test_cell -script"
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2014-09-06 11:46:07 +02:00 |
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Clifford Wolf
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652345c9cd
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Merge pull request #38 from rubund/master
Corrected spelling mistakes found by lintian
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2014-09-06 10:15:47 +02:00 |
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Ruben Undheim
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79cbf9067c
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Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
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Clifford Wolf
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01ef34c147
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Added tests/various/constmsk_test.ys
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2014-09-04 15:07:30 +02:00 |
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Clifford Wolf
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f5a40e7043
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Fixed "opt_const -fine" for $pos cells
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2014-09-04 08:55:58 +02:00 |
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Clifford Wolf
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8927aa6148
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Removed $bu0 cell type
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2014-09-04 02:07:52 +02:00 |
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Clifford Wolf
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b9cb483f3e
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Using $pos models for $bu0
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2014-09-03 21:20:59 +02:00 |
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Clifford Wolf
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5733f4a39d
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Fixed "test_cells -vlog"
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2014-09-03 13:43:37 +02:00 |
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Clifford Wolf
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50ac284823
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Fixes in $alu SAT- and eval-models
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2014-09-03 13:39:46 +02:00 |
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Clifford Wolf
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635b922afe
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Undef-related fixes in simlib $alu model
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2014-09-02 23:21:59 +02:00 |
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Clifford Wolf
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f1869667ca
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Improvements in "test_cell -vlog"
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2014-09-02 23:21:15 +02:00 |
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Clifford Wolf
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66bf2bb92e
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Added test_cell -vlog
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2014-09-02 22:49:43 +02:00 |
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Clifford Wolf
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da360771a1
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Create a default selection stack in RTLIL::Design::Design()
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2014-09-02 22:49:24 +02:00 |
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Clifford Wolf
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c38283dbd0
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Small bug fixes in $not, $neg, and $shiftx models
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2014-09-02 17:48:41 +02:00 |
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Clifford Wolf
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acd7a99aef
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Added SAT testing to test_cell eval stage
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2014-09-02 17:28:13 +02:00 |
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Clifford Wolf
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37fe7c7bdf
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Removed references to yosys-svgviewer from docs
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2014-09-02 04:03:06 +02:00 |
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