Clifford Wolf
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288ba9618a
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Moved common techlib files to techlibs/common
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2013-09-15 11:52:57 +02:00 |
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Clifford Wolf
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ad9bbcbf40
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Added $lut cells and abc lut mapping support
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2013-07-23 16:19:34 +02:00 |
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Clifford Wolf
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32dbf7752d
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Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
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2013-04-07 16:42:29 +02:00 |
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Clifford Wolf
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26f2439551
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Tiny bugfix in simlib.v
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2013-03-26 19:06:28 +01:00 |
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Clifford Wolf
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11789db206
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More support code for $sr cells
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2013-03-14 11:15:00 +01:00 |
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Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |
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