Clifford Wolf
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37aa2e02db
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AST simplifier: optimize constant AST_CASE nodes before recursively descending
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2014-10-29 08:29:51 +01:00 |
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Clifford Wolf
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c4a2b3c1e9
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Improvements in $readmem[bh] implementation
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2014-10-26 23:29:36 +01:00 |
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Clifford Wolf
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70b2efdb05
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Added support for $readmemh/$readmemb
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2014-10-26 20:33:10 +01:00 |
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Clifford Wolf
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26cbe4a4e5
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Fixed constant "cond ? string1 : string2" with strings of different size
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2014-10-25 18:23:53 +02:00 |
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Clifford Wolf
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750c615e7f
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minor indenting corrections
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2014-10-19 18:42:03 +02:00 |
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Parviz Palangpour
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de8adb8ec5
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Builds on Mac 10.9.2 with LLVM 3.5.
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2014-10-19 11:14:43 -05:00 |
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Clifford Wolf
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84ffe04075
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Fixed various VS warnings
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2014-10-18 15:20:38 +02:00 |
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William Speirs
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fda52f05f2
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Wrapped math in int constructor
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2014-10-17 11:28:14 +02:00 |
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Clifford Wolf
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6b05a9e807
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Fixed handling of invalid array access in mem2reg code
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2014-10-16 00:44:23 +02:00 |
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Clifford Wolf
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35fbc0b35f
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Do not the 'z' modifier in format string (another win32 fix)
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2014-10-11 11:42:08 +02:00 |
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Clifford Wolf
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4569a747f8
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Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
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Clifford Wolf
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f9a307a50b
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namespace Yosys
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2014-09-27 16:17:53 +02:00 |
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Clifford Wolf
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48b00dccea
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Another $clog2 bugfix
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2014-09-08 12:25:23 +02:00 |
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Clifford Wolf
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680eaaac41
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Fixed $clog2 (off by one error)
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2014-09-06 19:31:04 +02:00 |
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Clifford Wolf
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deff416ea7
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Fixed assignment of out-of bounds array element
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2014-09-06 17:58:27 +02:00 |
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Ruben Undheim
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79cbf9067c
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Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
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Clifford Wolf
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8927aa6148
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Removed $bu0 cell type
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2014-09-04 02:07:52 +02:00 |
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Clifford Wolf
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98442e019d
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Added emscripten (emcc) support to build system and some build fixes
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2014-08-22 16:20:22 +02:00 |
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Clifford Wolf
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74af3a2b70
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Archibald Rust and Clifford Wolf: ffi-based dpi_call()
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2014-08-22 14:22:09 +02:00 |
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Clifford Wolf
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ad146c2582
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Fixed small memory leak in ast simplify
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2014-08-21 17:33:40 +02:00 |
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Clifford Wolf
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6c5cafcd8b
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Added support for DPI function with different names in C and Verilog
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2014-08-21 17:22:04 +02:00 |
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Clifford Wolf
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085c8e873d
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Added AstNode::asInt()
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2014-08-21 17:11:51 +02:00 |
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Clifford Wolf
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490d7a5bf2
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Fixed memory leak in DPI function calls
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2014-08-21 13:09:47 +02:00 |
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Clifford Wolf
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7bfc4ae120
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Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
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2014-08-21 12:43:51 +02:00 |
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Clifford Wolf
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38addd4c67
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Added support for global tasks and functions
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2014-08-21 12:42:28 +02:00 |
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Clifford Wolf
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640d9fc551
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Added "via_celltype" attribute on task/func
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2014-08-18 14:29:30 +02:00 |
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Clifford Wolf
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acb435b6cf
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Added const folding of AST_CASE to AST simplifier
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2014-08-18 00:02:30 +02:00 |
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Clifford Wolf
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64713647a9
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Improved AST ProcessGenerator performance
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2014-08-17 02:17:49 +02:00 |
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Clifford Wolf
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d491fd8c19
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Use stackmap<> in AST ProcessGenerator
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2014-08-17 00:57:24 +02:00 |
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Clifford Wolf
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83e2698e10
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AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
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2014-08-16 19:31:59 +02:00 |
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Clifford Wolf
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c7afbd9d8e
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Fixed bug in "read_verilog -ignore_redef"
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2014-08-15 01:53:22 +02:00 |
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Clifford Wolf
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978a933b6a
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Added RTLIL::SigSpec::to_sigbit_map()
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2014-08-14 23:14:47 +02:00 |
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Clifford Wolf
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c83b990458
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Changed the AST genWidthRTLIL subst interface to use a std::map
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2014-08-14 23:02:07 +02:00 |
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Clifford Wolf
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85e3cc12ac
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Fixed handling of task outputs
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2014-08-14 22:26:10 +02:00 |
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Clifford Wolf
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1bf7a18fec
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Added module->ports
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2014-08-14 16:22:52 +02:00 |
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Clifford Wolf
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d259abbda2
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Added AST_MULTIRANGE (arrays with more than 1 dimension)
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2014-08-06 15:52:54 +02:00 |
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Clifford Wolf
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91dd87e60b
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Improved scope resolution of local regs in Verilog+AST frontend
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2014-08-05 12:15:53 +02:00 |
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Clifford Wolf
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0129d41efa
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Fixed AST handling of variables declared inside a functions main block
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2014-08-05 08:35:51 +02:00 |
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Clifford Wolf
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768eb846c4
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More bugfixes related to new RTLIL::IdString
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2014-08-02 18:14:21 +02:00 |
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Clifford Wolf
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b9bd22b8c8
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More cleanups related to RTLIL::IdString usage
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2014-08-02 13:19:57 +02:00 |
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Clifford Wolf
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14412e6c95
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Preparations for RTLIL::IdString redesign: cleanup of existing code
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2014-08-02 00:45:25 +02:00 |
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Clifford Wolf
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bd74ed7da4
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Replaced sha1 implementation
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2014-08-01 19:01:10 +02:00 |
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Clifford Wolf
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cdae8abe16
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Renamed port access function on RTLIL::Cell, added param access functions
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2014-07-31 16:38:54 +02:00 |
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Clifford Wolf
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e6d33513a5
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Added module->design and cell->module, wire->module pointers
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2014-07-31 14:11:39 +02:00 |
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Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
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Clifford Wolf
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397b00252d
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Added $shift and $shiftx cell types (needed for correct part select behavior)
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2014-07-29 16:35:13 +02:00 |
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Clifford Wolf
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48822e79a3
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Removed left over debug code
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2014-07-28 19:38:30 +02:00 |
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Clifford Wolf
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ec58965967
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Fixed part selects of parameters
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2014-07-28 19:24:28 +02:00 |
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Clifford Wolf
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a03297a7df
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Set results of out-of-bounds static bit/part select to undef
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2014-07-28 16:09:50 +02:00 |
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Clifford Wolf
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55521c085a
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Fixed RTLIL code generator for part select of parameter
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2014-07-28 15:31:19 +02:00 |
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