Clifford Wolf
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397b00252d
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Added $shift and $shiftx cell types (needed for correct part select behavior)
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2014-07-29 16:35:13 +02:00 |
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Clifford Wolf
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48822e79a3
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Removed left over debug code
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2014-07-28 19:38:30 +02:00 |
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Clifford Wolf
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ec58965967
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Fixed part selects of parameters
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2014-07-28 19:24:28 +02:00 |
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Clifford Wolf
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a03297a7df
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Set results of out-of-bounds static bit/part select to undef
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2014-07-28 16:09:50 +02:00 |
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Clifford Wolf
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55521c085a
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Fixed RTLIL code generator for part select of parameter
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2014-07-28 15:31:19 +02:00 |
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Clifford Wolf
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0598bc8708
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Fixed width detection for part selects
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2014-07-28 15:19:34 +02:00 |
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Clifford Wolf
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27a872d1e7
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
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Clifford Wolf
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3c45277ee0
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Added wire->upto flag for signals such as "wire [0:7] x;"
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2014-07-28 12:12:13 +02:00 |
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Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
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Clifford Wolf
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d86a25f145
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Added std::initializer_list<> constructor to SigSpec
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2014-07-28 10:52:58 +02:00 |
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Clifford Wolf
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f99495a895
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Added cover() to all SigSpec constructors
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2014-07-28 10:52:30 +02:00 |
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Clifford Wolf
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ee65dea738
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Fixed signdness detection of expressions with bit- and part-selects
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2014-07-28 10:10:08 +02:00 |
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Clifford Wolf
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c469be883b
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Improvements in tests/vloghtb
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2014-07-28 09:15:40 +02:00 |
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Clifford Wolf
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8b0f50792c
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Added techmap -extern
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2014-07-27 21:31:18 +02:00 |
|
Clifford Wolf
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c4bdba78cb
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Added proper Design->addModule interface
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2014-07-27 21:12:09 +02:00 |
|
Clifford Wolf
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5da343b7de
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Added topological sorting to techmap
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2014-07-27 16:43:39 +02:00 |
|
Clifford Wolf
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0c86d6106c
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Added SigPool::check(bit)
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2014-07-27 15:38:02 +02:00 |
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Clifford Wolf
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ddd31a0b66
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Small improvements in PerformanceTimer API
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2014-07-27 15:14:02 +02:00 |
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Clifford Wolf
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77a1462f2d
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Fixed bug in opt_clean
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2014-07-27 15:13:29 +02:00 |
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Clifford Wolf
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d07a871d35
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Improved performance of opt_const on large modules
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2014-07-27 14:50:25 +02:00 |
|
Clifford Wolf
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4be645860b
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Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
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2014-07-27 14:47:48 +02:00 |
|
Clifford Wolf
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cbc3a46a97
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Added RTLIL::SigSpecConstIterator
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2014-07-27 14:47:23 +02:00 |
|
Clifford Wolf
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dbb3556e3f
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Fixed a bug in opt_clean and some RTLIL API usage cleanups
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2014-07-27 13:19:05 +02:00 |
|
Clifford Wolf
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d878fcbdc7
|
Added log_cmd_error_expection
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2014-07-27 12:05:50 +02:00 |
|
Clifford Wolf
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7661ded8dd
|
Fixed verific bindings for new RTLIL api
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2014-07-27 12:00:28 +02:00 |
|
Clifford Wolf
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6b34215efd
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Fixed ilang parser for new RTLIL API
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2014-07-27 11:56:35 +02:00 |
|
Clifford Wolf
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49f72421d5
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Using new obj iterator API in a few places
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2014-07-27 11:32:42 +02:00 |
|
Clifford Wolf
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675cb93da9
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Added RTLIL::Module::wire(id) and cell(id) lookup functions
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2014-07-27 11:18:31 +02:00 |
|
Clifford Wolf
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0bd8fafbd2
|
Added RTLIL::Design::modules()
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2014-07-27 11:18:30 +02:00 |
|
Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
|
Clifford Wolf
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d088854b47
|
Added conversion from ObjRange to std::vector and std::set
|
2014-07-27 11:18:30 +02:00 |
|
Clifford Wolf
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1c8fdaeef8
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Added RTLIL::ObjIterator and RTLIL::ObjRange
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2014-07-27 11:18:30 +02:00 |
|
Clifford Wolf
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ddc5b41848
|
Using std::move() in SigSpec move constructor
|
2014-07-27 09:20:59 +02:00 |
|
Clifford Wolf
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7f3dc86ecd
|
Added RTLIL::SigSpec move constructor and move assignment operator
|
2014-07-27 02:11:57 +02:00 |
|
Clifford Wolf
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c91570bde3
|
Mostly cosmetic changes to rtlil.h
|
2014-07-27 02:00:04 +02:00 |
|
Clifford Wolf
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4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
|
Clifford Wolf
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f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
|
Clifford Wolf
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d7916a49af
|
New message for completion of build
|
2014-07-26 21:35:16 +02:00 |
|
Clifford Wolf
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d68c993ed2
|
Changed more code to the new RTLIL::Wire constructors
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2014-07-26 21:30:38 +02:00 |
|
Clifford Wolf
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946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
|
Clifford Wolf
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d49dec1f86
|
Added tests/various/.gitignore
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2014-07-26 17:43:41 +02:00 |
|
Clifford Wolf
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b21ebe1859
|
Added tests/various/submod_extract.ys
|
2014-07-26 17:22:18 +02:00 |
|
Clifford Wolf
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267c615640
|
Added support for here documents
|
2014-07-26 17:21:40 +02:00 |
|
Clifford Wolf
|
3f4e3ca8ad
|
More RTLIL::Cell API usage cleanups
|
2014-07-26 16:14:02 +02:00 |
|
Clifford Wolf
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97a59851a6
|
Added RTLIL::Cell::has(portname)
|
2014-07-26 16:11:28 +02:00 |
|
Clifford Wolf
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a84cb04935
|
Merge automatic and manual code changes for new cell connections API
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2014-07-26 16:00:30 +02:00 |
|
Clifford Wolf
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f8fdc47d33
|
Manual fixes for new cell connections API
|
2014-07-26 15:58:23 +02:00 |
|
Clifford Wolf
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b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
|
Clifford Wolf
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cd6574ecf6
|
Added some missing "const" in rtlil.h
|
2014-07-26 15:58:22 +02:00 |
|
Clifford Wolf
|
7ac9dc7f6e
|
Added RTLIL::Module::connections()
|
2014-07-26 15:58:21 +02:00 |
|