Clifford Wolf
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3a3f5d5923
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Progress in presentation
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2014-06-29 09:14:49 +02:00 |
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Clifford Wolf
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89c85cac41
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Added links to some liberty files to README
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2014-06-28 12:11:42 +02:00 |
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Clifford Wolf
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3e96ce8680
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Progress in presentation
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2014-06-26 22:05:39 +02:00 |
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Clifford Wolf
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076182c34e
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Fixed handling of mixed real/int ternary expressions
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2014-06-25 10:05:36 +02:00 |
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Clifford Wolf
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4fc43d1932
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More found_real-related fixes to AstNode::detectSignWidthWorker
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2014-06-24 15:08:48 +02:00 |
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Clifford Wolf
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a7aea17959
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Progress in presentation
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2014-06-22 12:50:29 +02:00 |
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Clifford Wolf
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3345fa0bab
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Little steps in realmath test bench
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2014-06-21 21:43:04 +02:00 |
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Clifford Wolf
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65b2e9c064
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fixed signdness detection for expressions with reals
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2014-06-21 21:41:13 +02:00 |
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Clifford Wolf
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072604f30f
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fixed typo
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2014-06-21 21:13:18 +02:00 |
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Clifford Wolf
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b18fa95d2f
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Progress in presentation
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2014-06-21 16:33:33 +02:00 |
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Clifford Wolf
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1c85584fe5
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Do not create $dffsr cells with no-op resets in proc_dff
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2014-06-19 12:29:29 +02:00 |
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Clifford Wolf
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df76da8fd7
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Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 21:49:59 +02:00 |
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Clifford Wolf
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80e4594695
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Added AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 21:39:25 +02:00 |
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Clifford Wolf
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798ff88855
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Improved handling of relational op of real values
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2014-06-17 12:47:51 +02:00 |
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Clifford Wolf
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88470283c9
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Little steps in realmath test bench
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2014-06-16 15:21:08 +02:00 |
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Clifford Wolf
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6c17d4f242
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Improved ternary support for real values
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2014-06-16 15:12:24 +02:00 |
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Clifford Wolf
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82bbd2f077
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Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
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2014-06-16 15:05:37 +02:00 |
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Clifford Wolf
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0c4c79c4c6
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Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
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2014-06-16 15:02:40 +02:00 |
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Clifford Wolf
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5bfe865cec
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Added found_real feature to AstNode::detectSignWidth
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2014-06-16 15:00:57 +02:00 |
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Clifford Wolf
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b1b96d199f
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Added more calls to "hierarchy" to README file
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2014-06-15 11:51:51 +02:00 |
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Clifford Wolf
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398482eced
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Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)
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2014-06-15 09:39:22 +02:00 |
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Clifford Wolf
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a4ec19c25c
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Added tests/realmath to "make test"
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2014-06-15 09:31:03 +02:00 |
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Clifford Wolf
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4d1df128fa
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Improved AstNode::realAsConst for large numbers
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2014-06-15 09:27:09 +02:00 |
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Clifford Wolf
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656685fa31
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Improved realmath test bench
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2014-06-15 08:48:41 +02:00 |
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Clifford Wolf
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7f57bc8385
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Improved parsing of large integer constants
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2014-06-15 08:48:17 +02:00 |
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Clifford Wolf
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48dc6ab98d
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Improved AstNode::asReal for large integers
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2014-06-15 08:38:31 +02:00 |
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Clifford Wolf
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11d2add1b9
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improved realmath test bench
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2014-06-14 21:00:51 +02:00 |
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Clifford Wolf
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149fe83a8d
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improved (fixed) conversion of real values to bit vectors
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2014-06-14 21:00:51 +02:00 |
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Clifford Wolf
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39eb347c67
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progress in realmath test bench
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2014-06-14 19:56:22 +02:00 |
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Clifford Wolf
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d5765b5e14
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Fixed relational operators for const real expressions
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2014-06-14 19:33:58 +02:00 |
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Clifford Wolf
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ebe2d73330
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added first draft of real math testcase generator
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2014-06-14 19:24:01 +02:00 |
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Clifford Wolf
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1a487303a0
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Progress in presentation
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2014-06-14 16:45:16 +02:00 |
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Clifford Wolf
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22a998903b
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Added %D and %c select commands
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2014-06-14 16:19:32 +02:00 |
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Clifford Wolf
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f3b4a9dd24
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Added support for math functions
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2014-06-14 13:36:23 +02:00 |
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Clifford Wolf
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406f86a91e
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Added realexpr.v test case
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2014-06-14 12:01:17 +02:00 |
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Clifford Wolf
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9bd7d5c468
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Added handling of real-valued parameters/localparams
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2014-06-14 12:00:47 +02:00 |
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Clifford Wolf
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fc7b6d172a
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Implemented more real arithmetic
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2014-06-14 11:27:05 +02:00 |
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Clifford Wolf
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442a8e2875
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Implemented basic real arithmetic
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2014-06-14 08:51:22 +02:00 |
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Clifford Wolf
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9dd16fa41c
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Added real->int convertion in ast genrtlil
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2014-06-14 07:44:19 +02:00 |
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Clifford Wolf
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7ef0da32cd
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Added Verilog lexer and parser support for real values
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2014-06-13 11:29:23 +02:00 |
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Clifford Wolf
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482d9208aa
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Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
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2014-06-12 11:54:20 +02:00 |
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Clifford Wolf
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9a6cd64fc2
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Now we are in Yoys 0.3.0+ development
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2014-06-08 15:31:27 +02:00 |
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Clifford Wolf
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ca125bf41b
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Tagging Yosys 0.3.0
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2014-06-08 15:28:36 +02:00 |
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Clifford Wolf
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94e9ee6bab
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Updated ABC to 7600ffb9340c
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2014-06-08 10:12:39 +02:00 |
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Clifford Wolf
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3af7c69d1e
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added tests for new verilog features
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2014-06-07 12:26:11 +02:00 |
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Clifford Wolf
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744e518467
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fixed cell array handling of positional arguments
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2014-06-07 12:17:11 +02:00 |
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Clifford Wolf
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e275e8eef9
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Add support for cell arrays
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2014-06-07 11:48:50 +02:00 |
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Clifford Wolf
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0b1ce63a19
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Added support for repeat stmt in const functions
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2014-06-07 10:47:53 +02:00 |
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Clifford Wolf
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7c8a7b2131
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further improved const function support
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2014-06-07 00:02:05 +02:00 |
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Clifford Wolf
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5281562d0e
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made the generate..endgenrate keywords optional
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2014-06-06 23:05:01 +02:00 |
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