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1369 commits 1 branch 6 tags 8.6 MiB
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105 commits

Author SHA1 Message Date
Clifford Wolf
3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf
7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf
97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf
f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf
5826670009 Various RTLIL::SigSpec related code cleanups 2014-07-25 14:25:42 +02:00
Clifford Wolf
6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf
c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf
a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf
ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf
28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf
4147b55c23 Added "autoidx" statement to ilang file format 2014-07-21 15:15:18 +02:00
Clifford Wolf
a30e2857c7 Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend 2014-07-20 02:16:30 +02:00
Clifford Wolf
0c67393313 Added support for $bu0 to verilog backend 2014-07-20 01:56:16 +02:00
Clifford Wolf
fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Clifford Wolf
f7bd0a5232 Use log_abort() and log_assert() in BTOR backend 2014-03-07 15:56:10 +01:00
Clifford Wolf
337b461d26 Added $lut support to blif backend (by user eddiehung from reddit) 2014-02-22 14:25:32 +01:00
Clifford Wolf
038eac7414 Better handling of nameDef and nameRef in edif backend 2014-02-21 13:40:43 +01:00
Clifford Wolf
f3ff29d410 Fixed instantiating multi-bit ports in edif backend 2014-02-21 13:10:36 +01:00
Clifford Wolf
79f8944811 Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param 2014-02-21 10:40:15 +01:00
Ahmed Irfan
ac896c63e2 modified btor synthesis script for correct use of splice command. 2014-02-12 13:38:28 +01:00
Ahmed Irfan
45e468114a disabling splice command in the script 2014-02-11 15:43:03 +01:00
Ahmed Irfan
1d64b3e008 register output corrected 2014-02-11 13:28:05 +01:00
Ahmed Irfan
e8f6b8f201 added concat and slice cell translation 2014-02-11 13:06:01 +01:00
Clifford Wolf
fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf
f4f230d7cc Fixed gcc compiler warnings with release build 2014-02-06 22:49:14 +01:00
Clifford Wolf
583636f0ad Added BTOR backend README file 2014-02-05 18:31:10 +01:00
Clifford Wolf
968ae31cac Added support for dump -append 2014-02-04 23:45:30 +01:00
Clifford Wolf
a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf
fa103e55ad Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys 2014-01-26 02:29:19 +01:00
Johann Glaser
f13b3518aa beautified write_intersynth 2014-01-25 20:16:38 +01:00
Ahmed Irfan
0325efe172 root bug corrected 2014-01-25 19:33:24 +01:00
Ahmed Irfan
137742786e removed regex include 2014-01-24 18:04:37 +01:00
Ahmed Irfan
2e44b1b73a merged clifford changes + removed regex 2014-01-24 17:35:42 +01:00
Clifford Wolf
210dda286f Use techmap -share_map in btor scripts 2014-01-24 15:52:16 +01:00
Clifford Wolf
6804edd5d4 Moved btor scripts to backends/btor/ 2014-01-24 15:48:07 +01:00
Ahmed Irfan
aa3cb20e1e slice bug corrected 2014-01-20 18:35:52 +01:00
Ahmed Irfan
c347f2825f assert feature 2014-01-20 10:45:02 +01:00
Ahmed Irfan
9a689f33a5 verilog default options pull 
shift operator width issues
 2014-01-17 19:32:35 +01:00
Ahmed Irfan
c7a2e582aa slice error corrected 2014-01-16 20:16:01 +01:00
Ahmed Irfan
3a1490888d width issues 
dff cell for more than one registers
 2014-01-15 17:36:33 +01:00
Ahmed Irfan
661b5a993e BTOR backend 2014-01-14 12:03:53 +01:00