Clifford Wolf
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c4e4f79a2a
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Disabled cover() for non-linux builds
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2014-07-25 12:27:36 +02:00 |
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Clifford Wolf
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7f1789ad1b
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Fixed typo in cover id
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2014-07-25 03:41:53 +02:00 |
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Clifford Wolf
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6aa792c864
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Replaced more old SigChunk programming patterns
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2014-07-24 23:10:58 +02:00 |
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Clifford Wolf
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10d2402e2f
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Added cover_list() API
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2014-07-24 20:47:18 +02:00 |
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Clifford Wolf
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2f54345cff
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Added "cover" command
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2014-07-24 16:14:19 +02:00 |
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Clifford Wolf
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e589289df7
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Some improvements in SigSpec packing/unpacking and checking
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2014-07-24 15:05:41 +02:00 |
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Clifford Wolf
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7679000673
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Now using a dedicated ELF section for all coverage counters
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2014-07-24 15:05:05 +02:00 |
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Clifford Wolf
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22ede43b3f
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Small changes regarding cover() and check() in SigSpec
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2014-07-24 04:46:36 +02:00 |
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Clifford Wolf
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798f713629
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Added support for YOSYS_COVER_FILE env variable
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2014-07-24 04:16:32 +02:00 |
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Clifford Wolf
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1b0d5fc22d
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Added cover() calls to RTLIL::SigSpec methods
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2014-07-24 03:50:28 +02:00 |
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Clifford Wolf
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9cf12570ba
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Added support for YOSYS_COVER_DIR env variable
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2014-07-24 03:49:32 +02:00 |
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Clifford Wolf
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6b1018314c
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Added cover() API
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2014-07-24 03:48:38 +02:00 |
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Clifford Wolf
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82fa356037
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Added hashing to RTLIL::SigSpec relational and equal operators
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2014-07-23 23:58:03 +02:00 |
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Clifford Wolf
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f368d792fb
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Disabled RTLIL::SigSpec::check() in release builds
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2014-07-23 21:42:44 +02:00 |
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Clifford Wolf
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95ac484548
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Fixed release build
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2014-07-23 21:38:18 +02:00 |
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Clifford Wolf
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2a41afb7b2
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Added RTLIL::SigSpec::repeat()
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2014-07-23 21:34:14 +02:00 |
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Clifford Wolf
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c094c53de8
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Removed RTLIL::SigSpec::optimize()
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2014-07-23 20:32:28 +02:00 |
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Clifford Wolf
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8fd8e4a468
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Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized
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2014-07-23 20:11:55 +02:00 |
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Clifford Wolf
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a62c21c9c6
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Removed RTLIL::SigSpec::expand() method
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2014-07-23 19:34:51 +02:00 |
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Clifford Wolf
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4e802eb7f6
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Fixed all users of SigSpec::chunks_rw() and removed it
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2014-07-23 15:36:09 +02:00 |
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Clifford Wolf
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85db102e13
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Replaced RTLIL::SigSpec::operator!=() with inline version
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2014-07-23 15:35:09 +02:00 |
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Clifford Wolf
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ec923652e2
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
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2014-07-23 09:52:55 +02:00 |
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Clifford Wolf
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a8d3a68971
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
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2014-07-23 09:49:43 +02:00 |
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Clifford Wolf
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260c19ec5a
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
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2014-07-23 09:34:47 +02:00 |
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Clifford Wolf
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c61467a32c
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Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)
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2014-07-23 08:59:54 +02:00 |
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Clifford Wolf
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115dd959d9
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SigSpec refactoring: More cleanups of old SigSpec use pattern
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2014-07-22 23:50:21 +02:00 |
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Clifford Wolf
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9e94f41b89
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SigSpec refactoring: Added RTLIL::SigSpecIterator
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2014-07-22 23:49:26 +02:00 |
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Clifford Wolf
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f80da7b41d
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SigSpec refactoring: added RTLIL::SigSpec::operator[]
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2014-07-22 22:54:03 +02:00 |
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Clifford Wolf
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fd4cbe6275
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SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form
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2014-07-22 22:26:30 +02:00 |
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Clifford Wolf
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a97be0828a
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Removed RTLIL::SigChunk::compare()
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2014-07-22 21:40:52 +02:00 |
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Clifford Wolf
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08e1e25169
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SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api
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2014-07-22 21:33:52 +02:00 |
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Clifford Wolf
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28b3fd05fa
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
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2014-07-22 20:58:44 +02:00 |
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Clifford Wolf
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7bffde6abd
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SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
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2014-07-22 20:39:38 +02:00 |
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Clifford Wolf
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4b4048bc5f
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SigSpec refactoring: using the accessor functions everywhere
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2014-07-22 20:39:37 +02:00 |
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Clifford Wolf
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16e5ae0b92
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SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions
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2014-07-22 20:39:37 +02:00 |
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Clifford Wolf
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a233762a81
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SigSpec refactoring: renamed chunks and width to __chunks and __width
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2014-07-22 20:39:37 +02:00 |
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Clifford Wolf
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550ac35873
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Added support for scripts with labels
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2014-07-21 13:28:18 +02:00 |
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Clifford Wolf
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361e0d62ff
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Replaced depricated NEW_WIRE macro with module->addWire() calls
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2014-07-21 12:42:02 +02:00 |
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Clifford Wolf
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1d88f1cf9f
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Removed deprecated module->new_wire()
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2014-07-21 12:35:06 +02:00 |
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Clifford Wolf
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c54d1f2ad1
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Bugfix in satgen for cells with wider in- than outputs.
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2014-07-21 12:03:41 +02:00 |
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Clifford Wolf
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54b0f2e659
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Added module->remove(), module->addWire(), module->addCell(), cell->check()
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2014-07-21 12:02:55 +02:00 |
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Clifford Wolf
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caae6e19df
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Added log_ping()
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2014-07-21 12:01:45 +02:00 |
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Clifford Wolf
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8d04ca7d22
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Added call_on_selection() and call_on_module() API
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2014-07-20 15:33:06 +02:00 |
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Clifford Wolf
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e57db5e9b2
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Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
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2014-07-20 11:01:04 +02:00 |
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Clifford Wolf
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efa7884026
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Added SIZE() macro
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2014-07-20 10:36:14 +02:00 |
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Clifford Wolf
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a6174aaf5e
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Added log_cell()
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2014-07-20 10:35:47 +02:00 |
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Clifford Wolf
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02f0acb3bc
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Fixed log_id() memory corruption
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2014-07-19 20:53:29 +02:00 |
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Clifford Wolf
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35edac0b31
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Added ModWalker helper class
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2014-07-19 15:33:00 +02:00 |
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Clifford Wolf
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1c288adcc0
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Some "const" cleanups in SigMap
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2014-07-19 15:32:39 +02:00 |
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Clifford Wolf
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a721f7d768
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Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>
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2014-07-18 11:36:34 +02:00 |
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