Clifford Wolf
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5733f4a39d
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Fixed "test_cells -vlog"
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2014-09-03 13:43:37 +02:00 |
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Clifford Wolf
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50ac284823
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Fixes in $alu SAT- and eval-models
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2014-09-03 13:39:46 +02:00 |
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Clifford Wolf
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635b922afe
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Undef-related fixes in simlib $alu model
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2014-09-02 23:21:59 +02:00 |
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Clifford Wolf
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f1869667ca
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Improvements in "test_cell -vlog"
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2014-09-02 23:21:15 +02:00 |
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Clifford Wolf
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66bf2bb92e
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Added test_cell -vlog
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2014-09-02 22:49:43 +02:00 |
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Clifford Wolf
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da360771a1
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Create a default selection stack in RTLIL::Design::Design()
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2014-09-02 22:49:24 +02:00 |
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Clifford Wolf
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c38283dbd0
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Small bug fixes in $not, $neg, and $shiftx models
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2014-09-02 17:48:41 +02:00 |
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Clifford Wolf
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acd7a99aef
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Added SAT testing to test_cell eval stage
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2014-09-02 17:28:13 +02:00 |
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Clifford Wolf
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37fe7c7bdf
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Removed references to yosys-svgviewer from docs
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2014-09-02 04:03:06 +02:00 |
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Clifford Wolf
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ee29ae2206
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Removed yosys-svgviewer
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2014-09-02 03:52:46 +02:00 |
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Clifford Wolf
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9f00a0cd2d
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Using "xdot" instead of "yosys-svgviewer" in show command
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2014-09-02 03:28:46 +02:00 |
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Clifford Wolf
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630befdf6d
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Added $alu support to test_cell
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2014-09-01 16:36:04 +02:00 |
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Clifford Wolf
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2fcf66b91d
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Added ConstEval model for $alu cells
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2014-09-01 16:35:46 +02:00 |
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Clifford Wolf
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bae09dca2b
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Added SAT model for $alu cells
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2014-09-01 16:35:25 +02:00 |
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Clifford Wolf
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9923762461
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Fixed "test_cell -simlib all"
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2014-09-01 15:37:56 +02:00 |
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Clifford Wolf
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c7f81e4e49
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Added "test_cell -simlib -v"
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2014-09-01 15:37:21 +02:00 |
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Clifford Wolf
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826fdb34d8
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Added "techmap -autoproc"
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2014-09-01 15:36:29 +02:00 |
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Clifford Wolf
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27a1bfbec6
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Fixes in old SAT example.ys
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2014-09-01 11:45:47 +02:00 |
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Clifford Wolf
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d5148f2e01
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Moved "share" and "wreduce" to passes/opt/
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2014-09-01 11:45:26 +02:00 |
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Clifford Wolf
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e07698818d
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Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
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2014-09-01 11:36:02 +02:00 |
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Clifford Wolf
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e3664066d5
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Added eval testing to test_cell
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2014-08-31 18:08:42 +02:00 |
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Clifford Wolf
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83ec3fa204
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Fixed return size of const_*() eval functions
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2014-08-31 18:08:26 +02:00 |
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Clifford Wolf
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be44157c0f
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Added RTLIL::Const::size()
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2014-08-31 18:07:48 +02:00 |
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Clifford Wolf
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a1c7d4a8e2
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Added eval model for $lut cells
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2014-08-31 17:43:31 +02:00 |
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Clifford Wolf
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0b6769af3f
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Typo fixes in cell->*Param() API
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2014-08-31 17:43:31 +02:00 |
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Clifford Wolf
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8649b57b6f
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Added $lut support in test_cell, techmap, satgen
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2014-08-31 17:43:31 +02:00 |
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Clifford Wolf
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2a1b08aeb3
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Added design->scratchpad
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2014-08-30 19:37:12 +02:00 |
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Clifford Wolf
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4724d94fbc
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Added $alu cell type
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2014-08-30 18:59:05 +02:00 |
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Clifford Wolf
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88db09255b
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Added autotest -e (do not use -noexpr on write_verilog)
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2014-08-30 18:34:07 +02:00 |
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Clifford Wolf
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6ff46323a3
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Improved write address decoder generation memory_map
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2014-08-30 18:18:15 +02:00 |
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Clifford Wolf
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dfbd7dd15a
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Fixed module->addPmux()
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2014-08-30 18:17:22 +02:00 |
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Clifford Wolf
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66763fad4e
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Using worker class in memory_map
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2014-08-30 17:39:08 +02:00 |
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Clifford Wolf
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eb571cba6a
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Replaced $__alu CO/CS outputs with full-width CO output
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2014-08-30 15:12:39 +02:00 |
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Clifford Wolf
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3a7d5d188d
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Don't change existing binary FSM encoding if it is already optimal
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2014-08-30 14:43:06 +02:00 |
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Clifford Wolf
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f910481f35
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Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
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2014-08-30 14:34:49 +02:00 |
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Clifford Wolf
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ab019b0bd5
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Improved handling of $pmux cells in fsm_extract
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2014-08-30 14:11:57 +02:00 |
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Clifford Wolf
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d148b0af0d
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Fixed inserting of Q-inverters in dfflibmap
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2014-08-27 19:44:12 +02:00 |
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Clifford Wolf
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cfb4338319
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Fixed printing of multi-line Makefile.conf
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2014-08-27 12:13:53 +02:00 |
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Clifford Wolf
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084685f480
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Implemented "rename -enumerate -pattern"
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2014-08-26 12:51:08 +02:00 |
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Clifford Wolf
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e70480655e
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Print Makefile.conf as make info message
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2014-08-26 10:11:46 +02:00 |
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Clifford Wolf
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672b2c6db1
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Checking for valid CONFIG value in Makefile
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2014-08-25 12:48:20 +02:00 |
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Clifford Wolf
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7bbbe3580d
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Optimize shift ops with constant rhs in opt_const
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2014-08-24 17:08:43 +02:00 |
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Clifford Wolf
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641501203c
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Added some additional log messages to opt_const
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2014-08-24 17:08:43 +02:00 |
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Clifford Wolf
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eda603105e
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Added is_signed argument to SigSpec.as_int() and Const.as_int()
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2014-08-24 15:14:00 +02:00 |
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Clifford Wolf
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9c5a63c52c
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azonenberg: Make dump_vcd save model when temporal induction fails due to step limit
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2014-08-24 13:27:40 +02:00 |
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Clifford Wolf
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c642dd0b3e
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Only call proc_share_dirname() in techmap when necessary
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2014-08-23 15:32:00 +02:00 |
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Clifford Wolf
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58367cd87a
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Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
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2014-08-23 15:14:58 +02:00 |
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Clifford Wolf
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19cff41eb4
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Changed frontend-api from FILE to std::istream
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2014-08-23 15:03:55 +02:00 |
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Clifford Wolf
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5dce303a2a
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Changed backend-api from FILE to std::ostream
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2014-08-23 13:54:21 +02:00 |
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Clifford Wolf
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fff12c719f
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Added "stat -width"
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2014-08-22 17:20:28 +02:00 |
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