stv0g/yosys
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1505 commits 1 branch 6 tags 8.6 MiB
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4 commits

Author SHA1 Message Date
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
5bf33de24a Added setattr and setparam commands 2014-02-05 11:11:55 +01:00