Clifford Wolf
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c4a2b3c1e9
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Improvements in $readmem[bh] implementation
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2014-10-26 23:29:36 +01:00 |
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Clifford Wolf
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70b2efdb05
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Added support for $readmemh/$readmemb
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2014-10-26 20:33:10 +01:00 |
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Clifford Wolf
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84ffe04075
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Fixed various VS warnings
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2014-10-18 15:20:38 +02:00 |
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William Speirs
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fda52f05f2
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Wrapped math in int constructor
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2014-10-17 11:28:14 +02:00 |
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Clifford Wolf
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6b05a9e807
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Fixed handling of invalid array access in mem2reg code
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2014-10-16 00:44:23 +02:00 |
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Clifford Wolf
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4569a747f8
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Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
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Clifford Wolf
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48b00dccea
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Another $clog2 bugfix
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2014-09-08 12:25:23 +02:00 |
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Clifford Wolf
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680eaaac41
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Fixed $clog2 (off by one error)
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2014-09-06 19:31:04 +02:00 |
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Ruben Undheim
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79cbf9067c
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Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
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Clifford Wolf
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ad146c2582
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Fixed small memory leak in ast simplify
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2014-08-21 17:33:40 +02:00 |
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Clifford Wolf
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6c5cafcd8b
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Added support for DPI function with different names in C and Verilog
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2014-08-21 17:22:04 +02:00 |
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Clifford Wolf
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490d7a5bf2
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Fixed memory leak in DPI function calls
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2014-08-21 13:09:47 +02:00 |
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Clifford Wolf
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7bfc4ae120
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Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
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2014-08-21 12:43:51 +02:00 |
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Clifford Wolf
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640d9fc551
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Added "via_celltype" attribute on task/func
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2014-08-18 14:29:30 +02:00 |
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Clifford Wolf
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acb435b6cf
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Added const folding of AST_CASE to AST simplifier
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2014-08-18 00:02:30 +02:00 |
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Clifford Wolf
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85e3cc12ac
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Fixed handling of task outputs
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2014-08-14 22:26:10 +02:00 |
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Clifford Wolf
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d259abbda2
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Added AST_MULTIRANGE (arrays with more than 1 dimension)
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2014-08-06 15:52:54 +02:00 |
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Clifford Wolf
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91dd87e60b
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Improved scope resolution of local regs in Verilog+AST frontend
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2014-08-05 12:15:53 +02:00 |
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Clifford Wolf
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0129d41efa
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Fixed AST handling of variables declared inside a functions main block
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2014-08-05 08:35:51 +02:00 |
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Clifford Wolf
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768eb846c4
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More bugfixes related to new RTLIL::IdString
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2014-08-02 18:14:21 +02:00 |
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Clifford Wolf
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14412e6c95
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Preparations for RTLIL::IdString redesign: cleanup of existing code
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2014-08-02 00:45:25 +02:00 |
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Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
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Clifford Wolf
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48822e79a3
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Removed left over debug code
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2014-07-28 19:38:30 +02:00 |
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Clifford Wolf
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ec58965967
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Fixed part selects of parameters
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2014-07-28 19:24:28 +02:00 |
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Clifford Wolf
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27a872d1e7
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
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Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
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Clifford Wolf
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309d64d46a
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Fixed two memory leaks in ast simplify
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2014-07-25 13:24:10 +02:00 |
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Clifford Wolf
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20a7965f61
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Various small fixes (from gcc compiler warnings)
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2014-07-23 20:45:27 +02:00 |
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Clifford Wolf
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9b183539af
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Implemented dynamic bit-/part-select for memory writes
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2014-07-17 16:49:23 +02:00 |
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Clifford Wolf
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5867f6bcdc
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Added support for bit/part select to mem2reg rewriter
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2014-07-17 13:49:32 +02:00 |
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Clifford Wolf
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6d69d4aaa8
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Added support for constant bit- or part-select for memory writes
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2014-07-17 13:13:21 +02:00 |
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Clifford Wolf
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543551b80a
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changes in verilog frontend for new $mem/$memwr WR_EN interface
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2014-07-16 12:49:50 +02:00 |
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Clifford Wolf
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55a1b8dbac
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Fixed processing of initial values for block-local variables
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2014-07-11 13:05:53 +02:00 |
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Clifford Wolf
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076182c34e
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Fixed handling of mixed real/int ternary expressions
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2014-06-25 10:05:36 +02:00 |
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Clifford Wolf
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80e4594695
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Added AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 21:39:25 +02:00 |
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Clifford Wolf
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798ff88855
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Improved handling of relational op of real values
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2014-06-17 12:47:51 +02:00 |
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Clifford Wolf
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6c17d4f242
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Improved ternary support for real values
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2014-06-16 15:12:24 +02:00 |
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Clifford Wolf
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82bbd2f077
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Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
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2014-06-16 15:05:37 +02:00 |
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Clifford Wolf
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48dc6ab98d
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Improved AstNode::asReal for large integers
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2014-06-15 08:38:31 +02:00 |
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Clifford Wolf
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149fe83a8d
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improved (fixed) conversion of real values to bit vectors
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2014-06-14 21:00:51 +02:00 |
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Clifford Wolf
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d5765b5e14
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Fixed relational operators for const real expressions
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2014-06-14 19:33:58 +02:00 |
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Clifford Wolf
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f3b4a9dd24
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Added support for math functions
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2014-06-14 13:36:23 +02:00 |
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Clifford Wolf
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9bd7d5c468
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Added handling of real-valued parameters/localparams
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2014-06-14 12:00:47 +02:00 |
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Clifford Wolf
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fc7b6d172a
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Implemented more real arithmetic
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2014-06-14 11:27:05 +02:00 |
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Clifford Wolf
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442a8e2875
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Implemented basic real arithmetic
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2014-06-14 08:51:22 +02:00 |
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Clifford Wolf
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e275e8eef9
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Add support for cell arrays
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2014-06-07 11:48:50 +02:00 |
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Clifford Wolf
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0b1ce63a19
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Added support for repeat stmt in const functions
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2014-06-07 10:47:53 +02:00 |
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Clifford Wolf
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7c8a7b2131
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further improved const function support
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2014-06-07 00:02:05 +02:00 |
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Clifford Wolf
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76da2fe172
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improved const function support
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2014-06-06 22:55:02 +02:00 |
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Clifford Wolf
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5c10d2ee36
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fix functions with no block (but single statement, loop, etc.)
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2014-06-06 21:29:23 +02:00 |
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