Ahmed Irfan
8acdd90bc9
Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor
2015-04-03 16:34:05 +02:00
Ahmed Irfan
7ad179151b
appnote for verilog to btor
2015-04-03 16:20:29 +02:00
Ahmed Irfan
d9444878cc
corrected abstract of appnote
2014-11-03 18:35:50 +01:00
Ahmed Irfan
6460d094e5
removed unused bib
...
removed unused bibitems from the appnote verilog to btor
2014-11-03 16:24:26 +01:00
Ahmed Irfan
3dd316bdc7
corrections in appnote
2014-11-03 16:18:53 +01:00
Ahmed Irfan
6c6cdf736a
appnote added
2014-11-03 13:23:35 +01:00
Ahmed Irfan
d3c67ad9b6
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
...
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation
Conflicts:
backends/btor/btor.cc
2014-09-22 11:35:04 +02:00
Clifford Wolf
13117bb346
Re-enabled assert for new logic loops in "share" pass
2014-09-21 19:44:08 +02:00
Clifford Wolf
96e821dc6c
Various improvements regarding logic loops in "share" results
2014-09-21 19:36:56 +02:00
Clifford Wolf
d6e2ace95b
Logic loop bugfix for "share" pass
2014-09-21 15:13:44 +02:00
Clifford Wolf
b28be0759f
Added "share -limit"
2014-09-21 15:13:06 +02:00
Clifford Wolf
a6c08b40fe
Still loop bug in "share": changed assert to warning
2014-09-21 14:51:07 +02:00
Clifford Wolf
8d60754aef
Do not introduce new logic loops in "share"
2014-09-21 13:52:39 +02:00
Clifford Wolf
edf11c635a
Assert on new logic loops in "share" pass
2014-09-21 12:57:33 +02:00
Clifford Wolf
a7758ef953
Added "test_abcloop" command
2014-09-19 15:51:34 +02:00
Clifford Wolf
00964f2f61
Initialize RTLIL::Const from std::vector<bool>
2014-09-19 15:50:55 +02:00
Clifford Wolf
309623ff17
Sorting of object names in ilang backend
2014-09-19 15:50:34 +02:00
Clifford Wolf
5827826098
Small improvements in "abc" command handle_loops() function
2014-09-19 14:05:41 +02:00
Clifford Wolf
3aa003c8e9
Using "NOT" instead of "INV" as cell name in default abc genlib file
2014-09-19 13:15:31 +02:00
Clifford Wolf
f7bb8f244b
Alphabetically sort port names in "show" output
2014-09-19 11:13:10 +02:00
Clifford Wolf
f56b92818b
Do not run "scorr" in "abc -fast"
2014-09-18 19:00:21 +02:00
Clifford Wolf
4888d61c65
Improvements in "synth" script
2014-09-18 12:57:55 +02:00
Clifford Wolf
815fab9d71
Added "abc -fast"
2014-09-18 12:57:37 +02:00
ahmedirfan1983
b783dbe148
fixed memory next issue, when same memory is written in different case statement
...
fixed reduce_xnor, logic_not bug translation bug
2014-09-18 11:19:48 +02:00
Clifford Wolf
ba61925071
Added commit count to devel version number
2014-09-17 07:19:34 +02:00
Clifford Wolf
9ae559b990
Fixed $_NOR vs. $_NOR_ typo in abc.cc
2014-09-16 12:45:05 +02:00
Clifford Wolf
ae02d9cb9a
Fixed $memwr/$memrd order in memory_dff
2014-09-16 12:40:58 +02:00
Clifford Wolf
fa96cf4a16
Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)
2014-09-16 11:26:44 +02:00
Clifford Wolf
6644e27cd4
Fixed $macc simlib model for zero-config
2014-09-16 08:19:35 +02:00
Clifford Wolf
b86410b2ab
More aggressive $macc merging in alumacc
2014-09-15 12:42:11 +02:00
Clifford Wolf
b470c480e9
Added the obvious optimizations to alumacc $macc generator
2014-09-15 12:22:03 +02:00
Clifford Wolf
fcbda07411
Improved maccmap tree bit packing
2014-09-15 12:00:19 +02:00
Clifford Wolf
2cbdbaad1f
Fixed wreduce $shiftx handling
2014-09-15 11:29:09 +02:00
Clifford Wolf
2442eb3832
Fixed monitor notifications for removed cell
2014-09-14 17:04:39 +02:00
Clifford Wolf
7815f81c32
Added "synth" command
2014-09-14 16:09:06 +02:00
Clifford Wolf
7e156a5419
Fixed techmap_wrap for techmap_celltype
2014-09-14 15:34:36 +02:00
Clifford Wolf
923bbbeaf0
Using alumacc in techmap.v
2014-09-14 14:50:15 +02:00
Clifford Wolf
014bb34e0e
Various fixes/cleanups in alumacc and maccmap
2014-09-14 14:49:53 +02:00
Clifford Wolf
124e759280
Added techmap_wrap attribute
2014-09-14 14:49:26 +02:00
Clifford Wolf
b34ca15185
alumacc fix for $pos cells
2014-09-14 14:00:14 +02:00
Clifford Wolf
0df1d9ad72
Extract $alu cells in alumacc
2014-09-14 13:23:44 +02:00
Clifford Wolf
7b16c63101
Merge $macc cells in alumacc pass
2014-09-14 11:21:37 +02:00
Clifford Wolf
0b72f0acb1
Basic $macc extract in alumacc
2014-09-14 10:45:28 +02:00
Clifford Wolf
ff157fb74f
alumacc skeleton
2014-09-14 10:02:00 +02:00
Clifford Wolf
aab0e3bf70
Cleanup in wreduce
2014-09-14 10:01:30 +02:00
Clifford Wolf
3ae96f85a5
Using pkg-config to find libffi
2014-09-13 17:28:15 +02:00
Clifford Wolf
44b5bd4b63
Fixed simlib $macc model for xilinx xsim
2014-09-08 17:09:39 +02:00
Clifford Wolf
fcb46138ce
Simplified $fa undef model
2014-09-08 16:59:39 +02:00
Clifford Wolf
6dc07eb1f2
Fixes and cleanups for blackbox.v
2014-09-08 13:31:04 +02:00
Clifford Wolf
af0c8873bb
Added $lcu cell type
2014-09-08 13:31:04 +02:00
