Clifford Wolf
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50f22ff30c
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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Clifford Wolf
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9b183539af
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Implemented dynamic bit-/part-select for memory writes
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2014-07-17 16:49:23 +02:00 |
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Clifford Wolf
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5867f6bcdc
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Added support for bit/part select to mem2reg rewriter
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2014-07-17 13:49:32 +02:00 |
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Clifford Wolf
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6d69d4aaa8
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Added support for constant bit- or part-select for memory writes
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2014-07-17 13:13:21 +02:00 |
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Clifford Wolf
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964a67ac41
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Added note to "make test": use git checkout of iverilog
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2014-07-16 10:03:07 +02:00 |
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Clifford Wolf
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ee8ad72fd9
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fixed parsing of constant with comment between size and value
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2014-07-02 06:27:04 +02:00 |
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Clifford Wolf
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076182c34e
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Fixed handling of mixed real/int ternary expressions
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2014-06-25 10:05:36 +02:00 |
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Clifford Wolf
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3345fa0bab
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Little steps in realmath test bench
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2014-06-21 21:43:04 +02:00 |
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Clifford Wolf
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df76da8fd7
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Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 21:49:59 +02:00 |
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Clifford Wolf
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398482eced
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Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)
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2014-06-15 09:39:22 +02:00 |
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Clifford Wolf
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a4ec19c25c
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Added tests/realmath to "make test"
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2014-06-15 09:31:03 +02:00 |
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Clifford Wolf
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f3b4a9dd24
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Added support for math functions
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2014-06-14 13:36:23 +02:00 |
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Clifford Wolf
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406f86a91e
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Added realexpr.v test case
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2014-06-14 12:01:17 +02:00 |
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Clifford Wolf
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3af7c69d1e
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added tests for new verilog features
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2014-06-07 12:26:11 +02:00 |
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Clifford Wolf
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c82db39935
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Added tests/simple/repwhile.v
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2014-06-06 17:47:20 +02:00 |
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Clifford Wolf
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a67cd2d4a2
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Progress in Verific bindings
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2014-03-17 01:56:00 +01:00 |
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Clifford Wolf
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a6750b3753
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
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Clifford Wolf
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4df7e03ec9
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Bugfix in name resolution with generate blocks
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2014-01-30 15:01:28 +01:00 |
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Clifford Wolf
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fb2bf934dc
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Added correct handling of $memwr priority
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2014-01-03 00:22:17 +01:00 |
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Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
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Clifford Wolf
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994c83db01
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Added multiplier test case from eda playground
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2013-12-18 13:43:53 +01:00 |
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Clifford Wolf
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fbd06a1afc
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Added elsif preproc support
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2013-12-18 13:41:36 +01:00 |
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Clifford Wolf
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921064c200
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Added support for macro arguments
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2013-12-18 13:21:02 +01:00 |
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Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
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Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
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Clifford Wolf
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a2d053694b
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Fix in sincos testbench gen
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2013-12-04 09:24:52 +01:00 |
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Clifford Wolf
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d1517b7982
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Added sincos test case
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2013-12-04 09:10:41 +01:00 |
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Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
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Clifford Wolf
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1e6836933d
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Added modelsim support to autotest
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2013-11-24 15:10:43 +01:00 |
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Clifford Wolf
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65ad556f3d
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Another name resolution bugfix for generate blocks
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2013-11-20 13:57:40 +01:00 |
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Clifford Wolf
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92035fb38e
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Implemented indexed part selects
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2013-11-20 13:05:27 +01:00 |
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Clifford Wolf
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19dba2561e
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Implemented part/bit select on memory read
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2013-11-20 10:51:32 +01:00 |
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Clifford Wolf
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c5e26f839c
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Added additional mem2reg testcase
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2013-11-18 19:55:39 +01:00 |
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Clifford Wolf
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2a25e3bca3
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Fixed parsing of default cases when not last case
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2013-11-18 16:10:50 +01:00 |
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Clifford Wolf
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fc6dc0d7b8
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Fixed handling of power operator
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2013-11-07 22:20:00 +01:00 |
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Clifford Wolf
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ada80545fa
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Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
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2013-11-02 21:13:01 +01:00 |
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Clifford Wolf
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943329c1dc
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Various ast changes for early expression width detection (prep for constfold fixes)
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2013-11-02 13:00:17 +01:00 |
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Clifford Wolf
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628b994cf6
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Added support for complex set-reset flip-flops in proc_dff
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2013-10-24 16:54:05 +02:00 |
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Clifford Wolf
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d61699843f
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Improved handling of dff with async resets
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2013-10-21 14:51:58 +02:00 |
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Clifford Wolf
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759852914d
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Added support for "2**n" shifter encoding
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2013-08-12 14:47:50 +02:00 |
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Clifford Wolf
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c8763301b4
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Added $div and $mod technology mapping
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2013-08-09 17:09:24 +02:00 |
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Clifford Wolf
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3650fd7fbe
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More fixes in ternary op sign handling
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2013-07-12 13:13:04 +02:00 |
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Clifford Wolf
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ded769c98c
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Fixed sign handling in ternary operator
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2013-07-12 01:15:37 +02:00 |
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Clifford Wolf
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b380c8c790
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Another vloghammer related bugfix
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2013-07-11 19:24:59 +02:00 |
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Clifford Wolf
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5dab327b30
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More fixes in ast expression sign/width handling
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2013-07-09 23:41:43 +02:00 |
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Clifford Wolf
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618b2ac994
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-07-09 19:00:10 +02:00 |
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Clifford Wolf
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7daeee340a
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Fixed shift ops with large right hand side
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2013-07-09 18:59:59 +02:00 |
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Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
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Clifford Wolf
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e8da3ea7b6
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Fixed another bug found using vloghammer
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2013-07-07 16:49:30 +02:00 |
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Clifford Wolf
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56432a920f
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
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