Clifford Wolf
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88fbdd4916
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Fixed algorithmic complexity of AST simplification of long expressions
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2014-01-20 20:25:20 +01:00 |
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Clifford Wolf
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1e67099b77
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Added $assert cell
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2014-01-19 14:03:40 +01:00 |
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Clifford Wolf
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9a1eb45c75
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Added Verilog parser support for asserts
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2014-01-19 04:18:22 +01:00 |
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Clifford Wolf
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13359d65ba
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Fixed parsing of verilog macros at end of line
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2014-01-18 19:22:20 +01:00 |
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Clifford Wolf
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6170cfe9cd
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Added verilog_defaults command
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2014-01-17 17:22:29 +01:00 |
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Clifford Wolf
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a3d94bf888
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Fixed typo in frontends/ast/simplify.cc
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2014-01-12 21:04:42 +01:00 |
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Clifford Wolf
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8f11eaaca6
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Added updating of RTLIL::autoidx to ilang frontend
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2014-01-03 17:51:05 +01:00 |
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Clifford Wolf
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fb2bf934dc
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Added correct handling of $memwr priority
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2014-01-03 00:22:17 +01:00 |
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Clifford Wolf
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364f277afb
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Fixed a stupid access after delete bug
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2013-12-29 20:18:22 +01:00 |
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Clifford Wolf
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1dcbba1abf
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Fixed parsing of non-arg macro calls followed by "("
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2013-12-27 16:25:27 +01:00 |
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Clifford Wolf
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72026a934e
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Fixed parsing of macros with no arguments and expansion text starting with "("
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2013-12-27 15:05:52 +01:00 |
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Clifford Wolf
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369bf81a70
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Added support for non-const === and !== (for miter circuits)
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2013-12-27 14:20:15 +01:00 |
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Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
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Clifford Wolf
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fbd06a1afc
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Added elsif preproc support
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2013-12-18 13:41:36 +01:00 |
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Clifford Wolf
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921064c200
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Added support for macro arguments
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2013-12-18 13:21:02 +01:00 |
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Clifford Wolf
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891e4b5b0d
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Keep strings as strings in const ternary and concat
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2013-12-05 13:26:17 +01:00 |
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Clifford Wolf
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e935bb6eda
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Added const folding support for $signed and $unsigned
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2013-12-05 13:09:41 +01:00 |
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Clifford Wolf
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5c39948ead
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Added AstNode::mkconst_str API
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2013-12-05 12:53:49 +01:00 |
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Clifford Wolf
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853538d78b
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Fixed generate-for (and disabled double warning for auto-wire)
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2013-12-04 21:33:00 +01:00 |
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Clifford Wolf
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3c220e0b32
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Added support for $clog2 system function
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2013-12-04 21:19:54 +01:00 |
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Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
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Clifford Wolf
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f4b46ed31e
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Replaced signed_parameters API with CONST_FLAG_SIGNED
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2013-12-04 14:24:44 +01:00 |
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Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
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Clifford Wolf
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507c63d112
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Added support for local regs in named blocks
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2013-12-04 09:10:16 +01:00 |
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Clifford Wolf
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10aa08dca1
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Fixed temp net name generation in rtlil process generator for abbreviated name matching
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2013-11-28 21:47:08 +01:00 |
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Clifford Wolf
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0e52f3fa01
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Added "src" attribute to processes
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2013-11-28 17:37:50 +01:00 |
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Clifford Wolf
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8dafecd34d
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Added module->avail_parameters (for advanced techmap features)
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2013-11-24 20:29:07 +01:00 |
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Clifford Wolf
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7d9a90396d
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Added verilog frontend -ignore_redef option
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2013-11-24 19:57:42 +01:00 |
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Clifford Wolf
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019b301541
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Early wire/reg/parameter width calculation in ast/simplify
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2013-11-24 19:40:23 +01:00 |
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Clifford Wolf
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0ef22c7609
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Added support for signed parameters in ilang
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2013-11-24 17:37:27 +01:00 |
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Clifford Wolf
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f71e27dbf1
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Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |
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Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
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Clifford Wolf
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1de12e1efc
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Improved handling of initialized registers
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2013-11-23 16:26:59 +01:00 |
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Clifford Wolf
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295e352ba6
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Renamed "placeholder" to "blackbox"
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2013-11-22 15:01:12 +01:00 |
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Clifford Wolf
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a362fd81ae
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Fixed O(n^2) performance bug in verilog preprocessor
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2013-11-22 14:08:43 +01:00 |
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Clifford Wolf
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e4429c480e
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Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
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2013-11-22 12:46:02 +01:00 |
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Clifford Wolf
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95c94a02fc
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Fixed async proc detection in mem2reg
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2013-11-21 21:26:56 +01:00 |
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Clifford Wolf
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09471846c5
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Major improvements in mem2reg and added "init" sync rules
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2013-11-21 13:49:00 +01:00 |
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Clifford Wolf
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08ceb3729e
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Fixed ilang parser: memory width
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2013-11-20 19:55:52 +01:00 |
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Clifford Wolf
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65ad556f3d
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Another name resolution bugfix for generate blocks
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2013-11-20 13:57:40 +01:00 |
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Clifford Wolf
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92035fb38e
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Implemented indexed part selects
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2013-11-20 13:05:27 +01:00 |
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Clifford Wolf
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c4c299eb5a
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Do not allow memory bit select on the left side of an assignment
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2013-11-20 12:18:46 +01:00 |
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Clifford Wolf
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0f04738f40
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Added "synthesis" in (synopsys|synthesis) comment support
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2013-11-20 11:44:09 +01:00 |
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Clifford Wolf
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ac2be2d892
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Fixed name resolution of local tasks and functions in generate block
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2013-11-20 11:05:58 +01:00 |
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Clifford Wolf
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19dba2561e
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Implemented part/bit select on memory read
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2013-11-20 10:51:32 +01:00 |
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Clifford Wolf
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e340532ce5
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Added init= attribute for fpga-style reset values
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2013-11-20 01:49:37 +01:00 |
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Clifford Wolf
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0dfdbd991a
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Fixed parsing of module arguments when one type is used for many args
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2013-11-19 20:35:31 +01:00 |
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Clifford Wolf
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4f2edcf2f9
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Fixed two bugs in mem2reg functionality in AST frontend
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2013-11-18 19:55:12 +01:00 |
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Clifford Wolf
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79910a5547
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Added dumping of attributes in AST frontend
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2013-11-18 19:54:36 +01:00 |
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Clifford Wolf
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2a25e3bca3
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Fixed parsing of default cases when not last case
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2013-11-18 16:10:50 +01:00 |
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