Clifford Wolf
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6d56172c0d
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Fixed line numbers when using here-doc macros
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2014-08-14 22:26:30 +02:00 |
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Clifford Wolf
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f53984795d
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Added support for non-standard """ macro bodies
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2014-08-13 13:03:38 +02:00 |
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Clifford Wolf
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2dc3333734
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Also allow "module foobar(input foo, output bar, ...);" syntax
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2014-08-07 16:41:27 +02:00 |
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Clifford Wolf
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d259abbda2
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Added AST_MULTIRANGE (arrays with more than 1 dimension)
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2014-08-06 15:52:54 +02:00 |
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Clifford Wolf
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91dd87e60b
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Improved scope resolution of local regs in Verilog+AST frontend
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2014-08-05 12:15:53 +02:00 |
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Clifford Wolf
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b5a3419ac2
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Added support for non-standard "module mod_name(...);" syntax
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2014-08-04 15:40:07 +02:00 |
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Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
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Clifford Wolf
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7daad40ca4
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Fixed counting verilog line numbers for "// synopsys translate_off" sections
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2014-07-30 20:18:48 +02:00 |
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Clifford Wolf
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e605af8a49
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Fixed Verilog pre-processor for files with no trailing newline
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2014-07-29 20:14:25 +02:00 |
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Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
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Clifford Wolf
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b17d6531c8
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Added "make PRETTY=1"
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2014-07-24 17:15:01 +02:00 |
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Clifford Wolf
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ee8ad72fd9
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fixed parsing of constant with comment between size and value
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2014-07-02 06:27:04 +02:00 |
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Clifford Wolf
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0c4c79c4c6
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Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
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2014-06-16 15:02:40 +02:00 |
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Clifford Wolf
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7f57bc8385
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Improved parsing of large integer constants
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2014-06-15 08:48:17 +02:00 |
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Clifford Wolf
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9bd7d5c468
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Added handling of real-valued parameters/localparams
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2014-06-14 12:00:47 +02:00 |
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Clifford Wolf
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7ef0da32cd
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Added Verilog lexer and parser support for real values
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2014-06-13 11:29:23 +02:00 |
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Clifford Wolf
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482d9208aa
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Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
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2014-06-12 11:54:20 +02:00 |
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Clifford Wolf
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e275e8eef9
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Add support for cell arrays
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2014-06-07 11:48:50 +02:00 |
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Clifford Wolf
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5281562d0e
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made the generate..endgenrate keywords optional
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2014-06-06 23:05:01 +02:00 |
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Clifford Wolf
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b5cd7a0179
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added while and repeat support to verilog parser
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2014-06-06 17:40:04 +02:00 |
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Clifford Wolf
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f9c1cd5edb
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Improved error message for options after front-end filename arguments
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2014-06-04 09:10:50 +02:00 |
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Clifford Wolf
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7188542155
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Fixed clang -Wdeprecated-register warnings
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2014-04-20 14:28:23 +02:00 |
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Clifford Wolf
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a1be4816d6
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Replaced depricated %name-prefix= bison directive
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2014-04-20 14:22:11 +02:00 |
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Clifford Wolf
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fad8558eb5
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Merged OSX fixes from Siesh1oo with some modifications
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2014-03-13 12:48:10 +01:00 |
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Clifford Wolf
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9992026a8d
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Added support for `line compiler directive
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2014-03-11 14:06:57 +01:00 |
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Clifford Wolf
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02e6f2c5be
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Added Verilog support for "`default_nettype none"
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2014-02-17 14:28:52 +01:00 |
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Clifford Wolf
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7d7e068dd1
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Added a warning note about error reporting to read_verilog help message
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2014-02-16 20:20:25 +01:00 |
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Clifford Wolf
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cd9e8741a7
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Implemented read_verilog -defer
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2014-02-13 13:59:13 +01:00 |
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Clifford Wolf
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007bdff55d
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Added support for functions returning integer
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2014-02-12 23:29:54 +01:00 |
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Clifford Wolf
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aa8e754ae5
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Added read_verilog -setattr
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2014-02-05 11:22:10 +01:00 |
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Clifford Wolf
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cdd6e11af5
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Added support for blanks after -I and -D in read_verilog
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2014-02-02 13:06:21 +01:00 |
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Clifford Wolf
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d06258f74f
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Added constant size expression support of sized constants
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2014-02-01 13:50:23 +01:00 |
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Clifford Wolf
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375c4dddc1
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Added read_verilog -icells option
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2014-01-29 00:59:28 +01:00 |
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Clifford Wolf
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0b47d907d3
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Fixed handling of unsized constants in verilog frontend
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2014-01-24 15:05:24 +01:00 |
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Clifford Wolf
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9a1eb45c75
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Added Verilog parser support for asserts
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2014-01-19 04:18:22 +01:00 |
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Clifford Wolf
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13359d65ba
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Fixed parsing of verilog macros at end of line
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2014-01-18 19:22:20 +01:00 |
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Clifford Wolf
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6170cfe9cd
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Added verilog_defaults command
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2014-01-17 17:22:29 +01:00 |
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Clifford Wolf
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1dcbba1abf
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Fixed parsing of non-arg macro calls followed by "("
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2013-12-27 16:25:27 +01:00 |
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Clifford Wolf
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72026a934e
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Fixed parsing of macros with no arguments and expansion text starting with "("
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2013-12-27 15:05:52 +01:00 |
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Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
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Clifford Wolf
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fbd06a1afc
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Added elsif preproc support
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2013-12-18 13:41:36 +01:00 |
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Clifford Wolf
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921064c200
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Added support for macro arguments
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2013-12-18 13:21:02 +01:00 |
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Clifford Wolf
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5c39948ead
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Added AstNode::mkconst_str API
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2013-12-05 12:53:49 +01:00 |
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Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
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Clifford Wolf
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507c63d112
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Added support for local regs in named blocks
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2013-12-04 09:10:16 +01:00 |
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Clifford Wolf
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7d9a90396d
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Added verilog frontend -ignore_redef option
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2013-11-24 19:57:42 +01:00 |
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Clifford Wolf
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1de12e1efc
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Improved handling of initialized registers
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2013-11-23 16:26:59 +01:00 |
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Clifford Wolf
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295e352ba6
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Renamed "placeholder" to "blackbox"
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2013-11-22 15:01:12 +01:00 |
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Clifford Wolf
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a362fd81ae
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Fixed O(n^2) performance bug in verilog preprocessor
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2013-11-22 14:08:43 +01:00 |
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Clifford Wolf
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e4429c480e
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Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
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2013-11-22 12:46:02 +01:00 |
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