ahmedirfan1983
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b783dbe148
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fixed memory next issue, when same memory is written in different case statement
fixed reduce_xnor, logic_not bug translation bug
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2014-09-18 11:19:48 +02:00 |
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Ahmed Irfan
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2446b6fbef
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added $pmux cell translation
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2014-09-02 14:47:51 +02:00 |
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Ahmed Irfan
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ac896c63e2
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modified btor synthesis script for correct use of splice command.
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2014-02-12 13:38:28 +01:00 |
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Ahmed Irfan
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45e468114a
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disabling splice command in the script
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2014-02-11 15:43:03 +01:00 |
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Ahmed Irfan
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1d64b3e008
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register output corrected
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2014-02-11 13:28:05 +01:00 |
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Ahmed Irfan
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1a2dc48c2a
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
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2014-02-11 13:26:43 +01:00 |
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Ahmed Irfan
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e8f6b8f201
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added concat and slice cell translation
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2014-02-11 13:06:01 +01:00 |
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Clifford Wolf
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d2fd45949d
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More Makefile cleanups
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2014-02-11 12:58:08 +01:00 |
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Clifford Wolf
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4bd2d47e45
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Improved "make manual" and "make clean"
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2014-02-11 12:55:58 +01:00 |
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Clifford Wolf
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fb186e6299
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Improved ilang parser error messages
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2014-02-09 15:35:31 +01:00 |
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Clifford Wolf
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d229324420
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fixed a bug in subcircuit library with cells that have connections to itself
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2014-02-09 15:27:58 +01:00 |
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Clifford Wolf
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38469e7686
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Various improvements in expose command (added -sep and -cut)
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2014-02-09 11:07:46 +01:00 |
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Clifford Wolf
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b6f33576d5
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Added delete {-input|-output|-port}
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2014-02-09 10:03:26 +01:00 |
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Clifford Wolf
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b3b5fac191
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Bugfix in delete command
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2014-02-09 09:34:58 +01:00 |
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Clifford Wolf
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039bb456cc
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Added test cases for expose -evert-dff
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2014-02-08 21:31:56 +01:00 |
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Clifford Wolf
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85914c36e5
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Fixed handling of async reset in expose -evert-dff
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2014-02-08 21:26:40 +01:00 |
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Clifford Wolf
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db86aaa07d
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Build fixes for log cmd
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2014-02-08 21:21:51 +01:00 |
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Clifford Wolf
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c06de50f05
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-08 21:08:46 +01:00 |
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Clifford Wolf
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0935e20003
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Implemented expose -evert-dff
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2014-02-08 21:08:38 +01:00 |
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Clifford Wolf
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793290a304
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Merge pull request #24 from hansiglaser/master
added "log" command
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2014-02-08 20:02:32 +01:00 |
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Johann Glaser
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af14bb5f65
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added "log" command
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2014-02-08 19:19:32 +01:00 |
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Clifford Wolf
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8f9c707a4c
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Improved checking of internal cell conventions
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2014-02-08 19:13:49 +01:00 |
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Clifford Wolf
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7f52c18a22
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Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
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2014-02-08 19:13:19 +01:00 |
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Clifford Wolf
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926fa61119
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Added various new options to splice command
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2014-02-08 16:37:18 +01:00 |
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Clifford Wolf
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0c11d04144
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Added %a select operator
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2014-02-08 16:31:38 +01:00 |
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Clifford Wolf
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6644f80d97
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Moved some passes to other source directories
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2014-02-08 14:39:15 +01:00 |
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Clifford Wolf
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03ee63ff80
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Added support for "keep" attribute to abc pass
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2014-02-08 14:25:29 +01:00 |
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Clifford Wolf
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82c98bbbe6
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Added opt -purge (frontend to opt_clean -purge)
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2014-02-08 14:21:34 +01:00 |
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Clifford Wolf
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922d1c9520
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Only count non-trivial attributes when findinf master signal in opt_clean
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2014-02-08 14:21:04 +01:00 |
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Clifford Wolf
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669a6e462d
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Added checking for ABC modifications to Makefile and made sure we do not have the word ERROR in regular make output
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2014-02-08 12:27:38 +01:00 |
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Clifford Wolf
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2c51619c2b
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Now also move net labes to the right position in splice cmd
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2014-02-08 00:06:00 +01:00 |
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Clifford Wolf
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274bcef66c
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Improved detection of primary wire for a signal in opt_clean
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2014-02-07 23:50:17 +01:00 |
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Clifford Wolf
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244e8ce1f4
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Added splice command
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2014-02-07 20:30:56 +01:00 |
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Clifford Wolf
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08aa1062b4
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Added log_header() to splitnets
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2014-02-07 19:51:15 +01:00 |
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Clifford Wolf
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d85a6bf5d3
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Added $slice and $concat to CellTypes list
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2014-02-07 19:50:44 +01:00 |
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Clifford Wolf
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fc3b3c4ec3
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Added $slice and $concat cell types
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2014-02-07 17:44:57 +01:00 |
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Clifford Wolf
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a1ac710ab8
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Stronger checking of internal cells
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2014-02-07 17:39:35 +01:00 |
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Clifford Wolf
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99b1e9ee56
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Re-enabled abc "retime" after sorting yout the yosys-bigsim problem
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2014-02-07 16:36:37 +01:00 |
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Clifford Wolf
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a51a3fa2d2
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Added echo command
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2014-02-07 14:17:00 +01:00 |
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Clifford Wolf
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366dcd3abf
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Fixed use of "cmd_error" in passes/cmds/design.cc
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2014-02-07 14:16:42 +01:00 |
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Clifford Wolf
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f4f230d7cc
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Fixed gcc compiler warnings with release build
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2014-02-06 22:49:14 +01:00 |
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Clifford Wolf
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0192f1c66e
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Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim failed)
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2014-02-06 22:31:58 +01:00 |
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Clifford Wolf
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a170d114a5
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Updated ABC to rev 10cc13a2a0f1
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2014-02-06 22:18:17 +01:00 |
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Clifford Wolf
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58cb8d65af
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Added "retime" to standard ABC recipes
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2014-02-06 22:16:20 +01:00 |
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Clifford Wolf
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91eab69912
|
Added copy command
|
2014-02-06 22:09:21 +01:00 |
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Clifford Wolf
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cf593222f2
|
Added design -stash/-copy-from/-copy-to
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2014-02-06 21:52:07 +01:00 |
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Clifford Wolf
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37fdb2ca7a
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Added support for s: select expressions (wire width)
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2014-02-06 19:45:03 +01:00 |
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Clifford Wolf
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9428050dd6
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Added i:, o:, and x: selection pattern
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2014-02-06 19:35:33 +01:00 |
|
Clifford Wolf
|
d7d1c7baf8
|
Added support for %m selection op
|
2014-02-06 19:30:08 +01:00 |
|
Clifford Wolf
|
f2fdcef13d
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-06 19:22:50 +01:00 |
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