Clifford Wolf
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8f9c707a4c
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Improved checking of internal cell conventions
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2014-02-08 19:13:49 +01:00 |
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Clifford Wolf
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d85a6bf5d3
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Added $slice and $concat to CellTypes list
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2014-02-07 19:50:44 +01:00 |
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Clifford Wolf
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fc3b3c4ec3
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Added $slice and $concat cell types
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2014-02-07 17:44:57 +01:00 |
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Clifford Wolf
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a1ac710ab8
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Stronger checking of internal cells
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2014-02-07 17:39:35 +01:00 |
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Clifford Wolf
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a51a3fa2d2
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Added echo command
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2014-02-07 14:17:00 +01:00 |
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Clifford Wolf
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fa295a4528
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Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
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2014-02-06 19:22:46 +01:00 |
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Clifford Wolf
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1c6dea3a0d
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Added support for #-comments in same line as command
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2014-02-06 14:26:39 +01:00 |
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Clifford Wolf
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19029f377b
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Added support for backslash continuation in script files
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2014-02-06 01:28:33 +01:00 |
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Clifford Wolf
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d267bcde4e
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Fixed bug in sequential sat proofs and improved handling of asserts
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2014-02-04 12:46:16 +01:00 |
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Clifford Wolf
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a6750b3753
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
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Clifford Wolf
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f9c4d33909
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Added RTLIL::SigSpec::to_single_sigbit()
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2014-02-02 21:35:26 +01:00 |
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Clifford Wolf
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672229eda5
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Added yosys -H for command list
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2014-01-30 12:32:59 +01:00 |
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Clifford Wolf
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96084e9864
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Added -h command line option
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2014-01-29 11:10:39 +01:00 |
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Clifford Wolf
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c36bac0e10
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Added $assert support to satgen
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2014-01-19 15:37:56 +01:00 |
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Clifford Wolf
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1e67099b77
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Added $assert cell
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2014-01-19 14:03:40 +01:00 |
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Clifford Wolf
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548d5aafa4
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Some improvements in log_dump_val_worker() templates
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2014-01-17 23:14:17 +01:00 |
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Clifford Wolf
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651ce67d97
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Added select -assert-none and -assert-any
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2014-01-17 16:34:50 +01:00 |
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Clifford Wolf
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7354a1718e
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Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux
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2014-01-03 17:30:50 +01:00 |
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Clifford Wolf
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eec2cd1e78
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Added RTLIL::SigSpec::optimized() API
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2014-01-03 02:43:31 +01:00 |
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Clifford Wolf
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fb2bf934dc
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Added correct handling of $memwr priority
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2014-01-03 00:22:17 +01:00 |
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Clifford Wolf
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1f80557ade
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Added SAT undef model for $pmux and $safe_pmux
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2014-01-02 19:58:59 +01:00 |
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Clifford Wolf
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249ef8695a
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Major rewrite of "freduce" command
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2014-01-02 16:52:33 +01:00 |
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Clifford Wolf
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15acf593e7
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Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
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2013-12-31 14:54:06 +01:00 |
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Clifford Wolf
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bf607df6d5
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Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)
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2013-12-29 17:39:49 +01:00 |
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Clifford Wolf
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c69c416d28
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Added $bu0 cell (for easy correct $eq/$ne mapping)
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2013-12-28 12:02:14 +01:00 |
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Clifford Wolf
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122b3c067b
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Fixed sat handling of $eqx and $nex with unequal port widths
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2013-12-27 18:11:05 +01:00 |
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Clifford Wolf
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0f5ab7649e
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Small cleanup in SatGen
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2013-12-27 15:18:14 +01:00 |
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Clifford Wolf
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ebf9abfeb6
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Fixed sat handling of $eqx and $nex cells
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2013-12-27 14:32:42 +01:00 |
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Clifford Wolf
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369bf81a70
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Added support for non-const === and !== (for miter circuits)
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2013-12-27 14:20:15 +01:00 |
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Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
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Clifford Wolf
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2ee3ac4ba3
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Added log_dump() API
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2013-12-20 12:11:58 +01:00 |
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Clifford Wolf
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8a815ac741
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Added "sat" undef support and "sat -set-init" options
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2013-12-07 17:28:51 +01:00 |
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Clifford Wolf
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ccf083e5b0
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Fixed uninitialized const flags bug
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2013-12-07 16:56:34 +01:00 |
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Clifford Wolf
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5d83904746
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Fixes and improvements in RTLIL::SigSpec::parse
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2013-12-07 11:57:29 +01:00 |
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Clifford Wolf
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f4b46ed31e
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Replaced signed_parameters API with CONST_FLAG_SIGNED
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2013-12-04 14:24:44 +01:00 |
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Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
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Clifford Wolf
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a66ca0472a
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Added Pass:call_newsel API
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2013-12-02 12:17:04 +01:00 |
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Clifford Wolf
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905eac04f1
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Added "history" command
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2013-12-02 11:29:39 +01:00 |
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Clifford Wolf
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1b3a60976d
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Using RTLIL::id2cstr for prompt printing
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2013-11-29 11:55:18 +01:00 |
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Clifford Wolf
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61412d167f
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Improvements in satgen undef handling
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2013-11-25 16:50:45 +01:00 |
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Clifford Wolf
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bd65e67d8a
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Improvements in satgen undef handling
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2013-11-25 15:12:01 +01:00 |
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Clifford Wolf
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8c3f4b3957
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Started implementing undef handling in satgen
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2013-11-25 04:51:33 +01:00 |
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Clifford Wolf
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8dafecd34d
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Added module->avail_parameters (for advanced techmap features)
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2013-11-24 20:29:07 +01:00 |
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Clifford Wolf
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f71e27dbf1
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Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |
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Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
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Clifford Wolf
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532091afcb
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Added more generic _TECHMAP_ wire mechanism to techmap pass
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2013-11-23 15:58:06 +01:00 |
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Clifford Wolf
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c854ad2e7e
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Some driver changes/fixes
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2013-11-22 14:53:57 +01:00 |
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Clifford Wolf
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058ceda6a0
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Added more performance measurement infrastructure
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2013-11-22 14:08:10 +01:00 |
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Clifford Wolf
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18d003254c
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Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
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2013-11-22 04:41:20 +01:00 |
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Clifford Wolf
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8e58bb330d
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Added SigBit struct and refactored RTLIL::SigSpec::extract
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2013-11-22 04:07:13 +01:00 |
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