Clifford Wolf
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4569a747f8
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Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
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Clifford Wolf
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c3e779a65f
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Added $_BUF_ cell type
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2014-10-03 10:12:28 +02:00 |
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Clifford Wolf
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af0c8873bb
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Added $lcu cell type
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2014-09-08 13:31:04 +02:00 |
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Clifford Wolf
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d46bac3305
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Added "$fa" cell type
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2014-09-08 12:15:39 +02:00 |
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Clifford Wolf
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b847ec8a0b
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Added $macc cell type
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2014-09-06 15:47:46 +02:00 |
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Clifford Wolf
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8927aa6148
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Removed $bu0 cell type
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2014-09-04 02:07:52 +02:00 |
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Clifford Wolf
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a1c7d4a8e2
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Added eval model for $lut cells
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2014-08-31 17:43:31 +02:00 |
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Clifford Wolf
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4724d94fbc
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Added $alu cell type
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2014-08-30 18:59:05 +02:00 |
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Clifford Wolf
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98442e019d
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Added emscripten (emcc) support to build system and some build fixes
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2014-08-22 16:20:22 +02:00 |
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Clifford Wolf
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47c2637a96
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Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
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2014-08-16 18:29:39 +02:00 |
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Clifford Wolf
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56a30cf42c
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Added CellTypes::cell_evaluable()
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2014-08-16 16:17:07 +02:00 |
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Clifford Wolf
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b64b38eea2
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Renamed $lut ports to follow A-Y naming scheme
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2014-08-15 14:18:40 +02:00 |
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Clifford Wolf
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f092b50148
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Renamed $_INV_ cell type to $_NOT_
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2014-08-15 14:11:40 +02:00 |
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Clifford Wolf
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1bf7a18fec
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Added module->ports
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2014-08-14 16:22:52 +02:00 |
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Clifford Wolf
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746aac540b
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Refactoring of CellType class
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2014-08-14 15:46:51 +02:00 |
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Clifford Wolf
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13f2f36884
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RIP $safe_pmux
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2014-08-14 11:39:46 +02:00 |
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Clifford Wolf
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14412e6c95
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Preparations for RTLIL::IdString redesign: cleanup of existing code
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2014-08-02 00:45:25 +02:00 |
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Clifford Wolf
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397b00252d
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Added $shift and $shiftx cell types (needed for correct part select behavior)
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2014-07-29 16:35:13 +02:00 |
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Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
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Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
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Clifford Wolf
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d4a1b0af5b
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Added support for dlatchsr cells
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2014-03-31 14:14:40 +02:00 |
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Clifford Wolf
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9e99984336
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Fixed const folding of $bu0 cells
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2014-02-27 04:09:32 +01:00 |
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Clifford Wolf
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d85a6bf5d3
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Added $slice and $concat to CellTypes list
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2014-02-07 19:50:44 +01:00 |
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Clifford Wolf
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fc3b3c4ec3
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Added $slice and $concat cell types
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2014-02-07 17:44:57 +01:00 |
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Clifford Wolf
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1e67099b77
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Added $assert cell
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2014-01-19 14:03:40 +01:00 |
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Clifford Wolf
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c69c416d28
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Added $bu0 cell (for easy correct $eq/$ne mapping)
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2013-12-28 12:02:14 +01:00 |
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Clifford Wolf
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369bf81a70
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Added support for non-const === and !== (for miter circuits)
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2013-12-27 14:20:15 +01:00 |
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Clifford Wolf
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e0f693cbb0
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Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
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2013-10-18 12:13:34 +02:00 |
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Clifford Wolf
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5998c101a4
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Added $sr, $dffsr and $dlatch cell types
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2013-10-18 11:56:16 +02:00 |
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Clifford Wolf
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ad9bbcbf40
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Added $lut cells and abc lut mapping support
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2013-07-23 16:19:34 +02:00 |
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Clifford Wolf
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6d7b5f9064
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Fixed even more ConstEval bugs found using xsthammer
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2013-06-14 17:50:26 +02:00 |
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Clifford Wolf
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30db70b1ba
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Added consteval testing to xsthammer and fixed bugs
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2013-06-13 19:51:13 +02:00 |
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Clifford Wolf
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ed0e2f7a6f
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Added log_assert() api
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2013-05-24 14:38:36 +02:00 |
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Clifford Wolf
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89f009d171
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Added additional functionality and cleanups in sigtools.h and celltypes.h
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2013-03-15 10:22:23 +01:00 |
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Clifford Wolf
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697cf1eb80
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Added #ci and #co selection operators
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2013-03-14 15:57:47 +01:00 |
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Clifford Wolf
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de823ce964
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Added $sr cell type to celltypes.h
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2013-03-14 01:08:30 +01:00 |
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Clifford Wolf
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65e5e1658c
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Added library support to celltypes class and show pass
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2013-03-03 10:36:23 +01:00 |
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Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |
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