Clifford Wolf
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e6d33513a5
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Added module->design and cell->module, wire->module pointers
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2014-07-31 14:11:39 +02:00 |
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Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
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Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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483c99fe46
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Added "design -push" and "design -pop"
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2014-02-20 23:28:59 +01:00 |
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Clifford Wolf
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366dcd3abf
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Fixed use of "cmd_error" in passes/cmds/design.cc
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2014-02-07 14:16:42 +01:00 |
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Clifford Wolf
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cf593222f2
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Added design -stash/-copy-from/-copy-to
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2014-02-06 21:52:07 +01:00 |
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Clifford Wolf
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0f38008ed3
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Added "design" command (-reset, -save, -load)
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2013-07-27 14:27:51 +02:00 |
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