Clifford Wolf
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8836943693
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Added yet another resource sharing test case
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2014-07-20 21:15:01 +02:00 |
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Clifford Wolf
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3b52121d32
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now ignore init attributes on non-register wires in sat command
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2014-07-05 11:18:38 +02:00 |
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Clifford Wolf
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482d9208aa
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Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
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2014-06-12 11:54:20 +02:00 |
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Clifford Wolf
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039bb456cc
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Added test cases for expose -evert-dff
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2014-02-08 21:31:56 +01:00 |
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Clifford Wolf
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244e8ce1f4
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Added splice command
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2014-02-07 20:30:56 +01:00 |
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Clifford Wolf
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849fd62cfe
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Added counters sat test case
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2014-02-06 01:00:56 +01:00 |
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Clifford Wolf
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7a66b38c3e
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Added test cases for sat command
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2014-02-04 13:43:34 +01:00 |
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