Clifford Wolf
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d2b083f5cb
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Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
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2013-11-03 18:56:45 +01:00 |
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Clifford Wolf
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ada80545fa
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Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
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2013-11-02 21:13:01 +01:00 |
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Clifford Wolf
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943329c1dc
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Various ast changes for early expression width detection (prep for constfold fixes)
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2013-11-02 13:00:17 +01:00 |
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Clifford Wolf
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23cf23418c
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Fixed handling of boolean attributes (frontends)
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2013-10-24 11:20:13 +02:00 |
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Clifford Wolf
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eae43e2db4
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Fixed handling of boolean attributes (kernel)
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2013-10-24 10:59:27 +02:00 |
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Clifford Wolf
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77726fb5fe
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Fixed parsing of value-less attributes in ilang
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2013-10-23 18:38:31 +02:00 |
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Johann Glaser
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f352205635
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fixed Verilog parser filename and line numbering issue with include files
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2013-08-21 09:20:59 +02:00 |
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Johann Glaser
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a99c224157
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Added support for include directories with the new '-I' argument of the
'read_verilog' command
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2013-08-20 15:48:16 +02:00 |
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Johann Glaser
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6c4cbc03c2
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Added support for notif0/notif1 primitives
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2013-08-20 11:23:59 +02:00 |
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Clifford Wolf
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0003743432
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Fixed width and sign detection for ** operator
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2013-08-19 20:58:01 +02:00 |
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Clifford Wolf
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8656b1c08f
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Added support for bufif0/bufif1 primitives
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2013-08-19 19:50:04 +02:00 |
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Clifford Wolf
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4214561890
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Improved ast dumping (ast/verilog frontend)
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2013-08-19 19:49:14 +02:00 |
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Clifford Wolf
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759852914d
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Added support for "2**n" shifter encoding
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2013-08-12 14:47:50 +02:00 |
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Clifford Wolf
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c8763301b4
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Added $div and $mod technology mapping
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2013-08-09 17:09:24 +02:00 |
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Clifford Wolf
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0f38008ed3
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Added "design" command (-reset, -save, -load)
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2013-07-27 14:27:51 +02:00 |
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Clifford Wolf
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3650fd7fbe
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More fixes in ternary op sign handling
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2013-07-12 13:13:04 +02:00 |
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Clifford Wolf
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ded769c98c
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Fixed sign handling in ternary operator
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2013-07-12 01:15:37 +02:00 |
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Clifford Wolf
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b380c8c790
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Another vloghammer related bugfix
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2013-07-11 19:24:59 +02:00 |
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Clifford Wolf
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ed62fcdbe2
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Fixed sign propagation in bit-wise operators
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2013-07-09 23:53:55 +02:00 |
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Clifford Wolf
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5dab327b30
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More fixes in ast expression sign/width handling
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2013-07-09 23:41:43 +02:00 |
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Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
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Clifford Wolf
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e8da3ea7b6
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Fixed another bug found using vloghammer
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2013-07-07 16:49:30 +02:00 |
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Clifford Wolf
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eff68560a2
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Fixed AST_CONSTANT node generation
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2013-07-07 15:40:26 +02:00 |
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Clifford Wolf
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56432a920f
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
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Clifford Wolf
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0c6ffc4c65
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More fixes for bugs found using xsthammer
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2013-06-13 11:18:45 +02:00 |
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Clifford Wolf
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4b311b7b99
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Further improved and extended xsthammer
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2013-06-11 19:49:35 +02:00 |
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Clifford Wolf
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a5c30183b5
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Sign-extension related fixes in SatGen and AST frontend
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2013-06-10 17:10:06 +02:00 |
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Clifford Wolf
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59dd02baa2
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Fixes and improvements in AST const folding
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2013-06-10 13:56:03 +02:00 |
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Clifford Wolf
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db98a18edb
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Enabled AST/Verilog front-end optimizations per default
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2013-06-10 13:19:04 +02:00 |
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Clifford Wolf
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46fbe9d262
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Added SAT generator and simple sat_solve command
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2013-06-07 13:59:13 +02:00 |
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Clifford Wolf
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ed0e2f7a6f
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Added log_assert() api
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2013-05-24 14:38:36 +02:00 |
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Clifford Wolf
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375f83c5ec
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Fixed memory leak in ilang frontend
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2013-05-23 12:55:59 +02:00 |
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Johann Glaser
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10a195c0a1
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added option '-Dname[=definition]' to command 'read_verilog'
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2013-05-19 17:07:52 +02:00 |
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Clifford Wolf
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c5ee2b306a
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Merge branch 'bugfix'
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2013-05-16 16:44:45 +02:00 |
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Clifford Wolf
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6cc8e848b6
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Fixed synthesis of functions in latched blocks
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2013-05-16 16:44:06 +02:00 |
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Clifford Wolf
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b56e06d2f5
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Added support for verilog === operator
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2013-05-07 14:35:40 +02:00 |
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Clifford Wolf
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8f2d90de4f
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Fixed handling of positional module parameters
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2013-04-26 14:40:25 +02:00 |
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Clifford Wolf
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453a29c9f6
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Only use sha1 checksums for names of parametric modules when the verbose form is to long
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2013-04-26 13:13:58 +02:00 |
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Clifford Wolf
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e0c408cb4a
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Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
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2013-04-13 21:19:10 +02:00 |
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Clifford Wolf
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f1a2fd966f
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Now only use value from "initial" when no matching "always" block is found
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2013-03-31 11:51:12 +02:00 |
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Clifford Wolf
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161565be10
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
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2013-03-31 11:19:11 +02:00 |
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Clifford Wolf
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7bfc7b61a8
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Implemented proper handling of stub placeholder modules
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2013-03-28 09:20:10 +01:00 |
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Clifford Wolf
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7a99349de4
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Improvements and bugfixes for generate blocks with local signals
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2013-03-26 11:31:34 +01:00 |
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Clifford Wolf
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6a382f2aba
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Fixed handling of unconditional generate blocks
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2013-03-26 09:44:54 +01:00 |
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Clifford Wolf
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227520f94d
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Added nosync attribute and some async reset related fixes
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2013-03-25 17:13:14 +01:00 |
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Clifford Wolf
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df9753d398
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Added mem2reg option to verilog frontend
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2013-03-24 11:13:32 +01:00 |
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Clifford Wolf
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3a5244e913
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Another fix in mem2reg ast simplify logic
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2013-03-24 10:42:08 +01:00 |
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Clifford Wolf
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bb3357c027
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Improved mem2reg handling in ast simplifier
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2013-03-24 09:27:01 +01:00 |
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Clifford Wolf
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e45d1c8865
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Tiny fixes to verilog parser
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2013-03-23 18:54:31 +01:00 |
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Clifford Wolf
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8a6b0a3520
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Added help messages to ilang and verilog frontends
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2013-03-01 08:03:00 +01:00 |
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