Clifford Wolf
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f9c4d33909
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Added RTLIL::SigSpec::to_single_sigbit()
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2014-02-02 21:35:26 +01:00 |
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Clifford Wolf
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651ce67d97
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Added select -assert-none and -assert-any
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2014-01-17 16:34:50 +01:00 |
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Clifford Wolf
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eec2cd1e78
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Added RTLIL::SigSpec::optimized() API
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2014-01-03 02:43:31 +01:00 |
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Clifford Wolf
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c69c416d28
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Added $bu0 cell (for easy correct $eq/$ne mapping)
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2013-12-28 12:02:14 +01:00 |
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Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
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Clifford Wolf
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ccf083e5b0
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Fixed uninitialized const flags bug
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2013-12-07 16:56:34 +01:00 |
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Clifford Wolf
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f4b46ed31e
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Replaced signed_parameters API with CONST_FLAG_SIGNED
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2013-12-04 14:24:44 +01:00 |
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Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
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Clifford Wolf
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8dafecd34d
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Added module->avail_parameters (for advanced techmap features)
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2013-11-24 20:29:07 +01:00 |
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Clifford Wolf
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f71e27dbf1
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Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |
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Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
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Clifford Wolf
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532091afcb
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Added more generic _TECHMAP_ wire mechanism to techmap pass
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2013-11-23 15:58:06 +01:00 |
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Clifford Wolf
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8e58bb330d
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Added SigBit struct and refactored RTLIL::SigSpec::extract
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2013-11-22 04:07:13 +01:00 |
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Clifford Wolf
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09471846c5
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Major improvements in mem2reg and added "init" sync rules
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2013-11-21 13:49:00 +01:00 |
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Clifford Wolf
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223892ac28
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Improved user-friendliness of "sat" and "eval" expression parsing
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2013-11-09 12:02:27 +01:00 |
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Clifford Wolf
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947bd9b96b
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Renamed extend_un0() to extend_u0() and use it in genrtlil
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2013-11-07 18:17:10 +01:00 |
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Clifford Wolf
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0e1661f84e
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Fixed type of sign extension in opt_const $eq/$ne handling
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2013-11-07 16:53:28 +01:00 |
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Clifford Wolf
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bd2c8ec886
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Added design->full_selection() helper method
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2013-10-27 09:30:58 +01:00 |
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Clifford Wolf
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e679a5d046
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Fixed handling of boolean attributes (passes)
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2013-10-24 11:37:54 +02:00 |
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Clifford Wolf
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eae43e2db4
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Fixed handling of boolean attributes (kernel)
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2013-10-24 10:59:27 +02:00 |
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Clifford Wolf
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8e8f1994b8
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Changed NEW_WIRE API to return the wire, not the signal
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2013-10-18 14:19:45 +02:00 |
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Clifford Wolf
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cc5e379eca
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Added RTLIL NEW_WIRE macro
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2013-10-18 13:25:24 +02:00 |
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Clifford Wolf
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376150c926
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Added techmap -opt mode
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2013-08-09 15:20:22 +02:00 |
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Clifford Wolf
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05483619f0
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Some fixes to improve determinism
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2013-08-09 12:42:32 +02:00 |
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Clifford Wolf
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0f38008ed3
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Added "design" command (-reset, -save, -load)
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2013-07-27 14:27:51 +02:00 |
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Clifford Wolf
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21e38bed98
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Added "eval" pass
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2013-06-19 09:30:37 +02:00 |
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Clifford Wolf
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a046a302f0
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Fixed build with clang
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2013-06-18 19:54:33 +02:00 |
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Clifford Wolf
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6971c4db62
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Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
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2013-06-18 17:11:13 +02:00 |
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Clifford Wolf
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21d9251e52
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Added "dump" command (part ilang backend)
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2013-06-02 17:53:30 +02:00 |
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Clifford Wolf
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88af5b6a16
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Improved opt_share for reduce cells
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2013-03-29 11:19:21 +01:00 |
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Clifford Wolf
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d4680fd5a0
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Added design->select() api and use it in extract pass
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2013-03-03 20:53:24 +01:00 |
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Clifford Wolf
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1bc0f04789
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Added id2cstr API
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2013-03-01 09:01:49 +01:00 |
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Clifford Wolf
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51c2b797b3
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Do not unescape identifiers starting with \$
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2013-03-01 01:10:11 +01:00 |
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Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |
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