Clifford Wolf
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9bd7d5c468
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Added handling of real-valued parameters/localparams
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2014-06-14 12:00:47 +02:00 |
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Clifford Wolf
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442a8e2875
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Implemented basic real arithmetic
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2014-06-14 08:51:22 +02:00 |
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Clifford Wolf
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7ef0da32cd
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Added Verilog lexer and parser support for real values
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2014-06-13 11:29:23 +02:00 |
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Clifford Wolf
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e275e8eef9
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Add support for cell arrays
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2014-06-07 11:48:50 +02:00 |
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Clifford Wolf
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b5cd7a0179
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added while and repeat support to verilog parser
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2014-06-06 17:40:04 +02:00 |
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Clifford Wolf
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09805ee9ec
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Include id2ast pointers when dumping AST
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2014-03-05 19:56:31 +01:00 |
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Clifford Wolf
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4bd25edcd4
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Cleanups in handling of read_verilog -defer and -icells
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2014-02-20 19:12:32 +01:00 |
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Clifford Wolf
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02e6f2c5be
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Added Verilog support for "`default_nettype none"
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2014-02-17 14:28:52 +01:00 |
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Clifford Wolf
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e8af3def7f
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Added support for FOR loops in function calls in parameters
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2014-02-14 20:33:22 +01:00 |
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Clifford Wolf
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534c1a5dd0
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Created basic support for function calls in parameter values
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2014-02-14 19:56:44 +01:00 |
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Clifford Wolf
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cd9e8741a7
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Implemented read_verilog -defer
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2014-02-13 13:59:13 +01:00 |
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Clifford Wolf
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d06258f74f
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Added constant size expression support of sized constants
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2014-02-01 13:50:23 +01:00 |
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Clifford Wolf
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375c4dddc1
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Added read_verilog -icells option
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2014-01-29 00:59:28 +01:00 |
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Clifford Wolf
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88fbdd4916
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Fixed algorithmic complexity of AST simplification of long expressions
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2014-01-20 20:25:20 +01:00 |
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Clifford Wolf
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9a1eb45c75
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Added Verilog parser support for asserts
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2014-01-19 04:18:22 +01:00 |
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Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
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Clifford Wolf
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891e4b5b0d
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Keep strings as strings in const ternary and concat
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2013-12-05 13:26:17 +01:00 |
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Clifford Wolf
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5c39948ead
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Added AstNode::mkconst_str API
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2013-12-05 12:53:49 +01:00 |
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Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
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Clifford Wolf
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f4b46ed31e
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Replaced signed_parameters API with CONST_FLAG_SIGNED
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2013-12-04 14:24:44 +01:00 |
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Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
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Clifford Wolf
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7d9a90396d
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Added verilog frontend -ignore_redef option
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2013-11-24 19:57:42 +01:00 |
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Clifford Wolf
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f71e27dbf1
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Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |
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Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
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Clifford Wolf
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295e352ba6
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Renamed "placeholder" to "blackbox"
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2013-11-22 15:01:12 +01:00 |
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Clifford Wolf
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79910a5547
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Added dumping of attributes in AST frontend
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2013-11-18 19:54:36 +01:00 |
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Clifford Wolf
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378cc509cd
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Call internal checker more often
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2013-11-10 23:24:21 +01:00 |
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Clifford Wolf
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f050c40519
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Various fixes for correct parameter support
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2013-11-07 10:02:11 +01:00 |
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Clifford Wolf
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943329c1dc
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Various ast changes for early expression width detection (prep for constfold fixes)
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2013-11-02 13:00:17 +01:00 |
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Clifford Wolf
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23cf23418c
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Fixed handling of boolean attributes (frontends)
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2013-10-24 11:20:13 +02:00 |
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Clifford Wolf
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4214561890
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Improved ast dumping (ast/verilog frontend)
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2013-08-19 19:49:14 +02:00 |
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Clifford Wolf
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0f38008ed3
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Added "design" command (-reset, -save, -load)
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2013-07-27 14:27:51 +02:00 |
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Clifford Wolf
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eff68560a2
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Fixed AST_CONSTANT node generation
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2013-07-07 15:40:26 +02:00 |
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Clifford Wolf
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56432a920f
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
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Clifford Wolf
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db98a18edb
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Enabled AST/Verilog front-end optimizations per default
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2013-06-10 13:19:04 +02:00 |
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Clifford Wolf
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ed0e2f7a6f
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Added log_assert() api
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2013-05-24 14:38:36 +02:00 |
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Clifford Wolf
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8f2d90de4f
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Fixed handling of positional module parameters
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2013-04-26 14:40:25 +02:00 |
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Clifford Wolf
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453a29c9f6
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Only use sha1 checksums for names of parametric modules when the verbose form is to long
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2013-04-26 13:13:58 +02:00 |
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Clifford Wolf
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f1a2fd966f
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Now only use value from "initial" when no matching "always" block is found
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2013-03-31 11:51:12 +02:00 |
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Clifford Wolf
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161565be10
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
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2013-03-31 11:19:11 +02:00 |
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Clifford Wolf
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7bfc7b61a8
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Implemented proper handling of stub placeholder modules
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2013-03-28 09:20:10 +01:00 |
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Clifford Wolf
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df9753d398
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Added mem2reg option to verilog frontend
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2013-03-24 11:13:32 +01:00 |
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Clifford Wolf
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a321a5c412
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Moved stand-alone libs to libs/ directory and added libs/subcircuit
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2013-02-27 09:32:19 +01:00 |
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Clifford Wolf
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4f0c2862a0
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Added support for verilog genblock[index].member syntax
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2013-02-26 13:18:22 +01:00 |
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Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |
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