4 commits

Author	SHA1	Message	Date
Clifford Wolf	0b47d907d3	Fixed handling of unsized constants in verilog frontend	2014-01-24 15:05:24 +01:00
Clifford Wolf	00a6c1d9a5	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
Clifford Wolf	46fbe9d262	Added SAT generator and simple sat_solve command	2013-06-07 13:59:13 +02:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00