Clifford Wolf
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ee65dea738
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Fixed signdness detection of expressions with bit- and part-selects
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2014-07-28 10:10:08 +02:00 |
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Clifford Wolf
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c4bdba78cb
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Added proper Design->addModule interface
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2014-07-27 21:12:09 +02:00 |
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Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
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Clifford Wolf
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946ddff9ce
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Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26 20:12:50 +02:00 |
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Clifford Wolf
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f8fdc47d33
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Manual fixes for new cell connections API
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2014-07-26 15:58:23 +02:00 |
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Clifford Wolf
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b7dda72302
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
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2014-07-26 15:58:23 +02:00 |
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Clifford Wolf
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cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
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Clifford Wolf
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2bec47a404
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Use only module->addCell() and module->remove() to create and delete cells
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2014-07-25 17:56:19 +02:00 |
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Clifford Wolf
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309d64d46a
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Fixed two memory leaks in ast simplify
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2014-07-25 13:24:10 +02:00 |
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Clifford Wolf
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6aa792c864
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Replaced more old SigChunk programming patterns
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2014-07-24 23:10:58 +02:00 |
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Clifford Wolf
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20a7965f61
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Various small fixes (from gcc compiler warnings)
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2014-07-23 20:45:27 +02:00 |
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Clifford Wolf
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c094c53de8
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Removed RTLIL::SigSpec::optimize()
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2014-07-23 20:32:28 +02:00 |
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Clifford Wolf
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115dd959d9
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SigSpec refactoring: More cleanups of old SigSpec use pattern
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2014-07-22 23:50:21 +02:00 |
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Clifford Wolf
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28b3fd05fa
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
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2014-07-22 20:58:44 +02:00 |
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Clifford Wolf
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7bffde6abd
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SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
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2014-07-22 20:39:38 +02:00 |
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Clifford Wolf
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4b4048bc5f
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SigSpec refactoring: using the accessor functions everywhere
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2014-07-22 20:39:37 +02:00 |
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Clifford Wolf
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a233762a81
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SigSpec refactoring: renamed chunks and width to __chunks and __width
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2014-07-22 20:39:37 +02:00 |
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Clifford Wolf
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9b183539af
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Implemented dynamic bit-/part-select for memory writes
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2014-07-17 16:49:23 +02:00 |
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Clifford Wolf
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5867f6bcdc
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Added support for bit/part select to mem2reg rewriter
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2014-07-17 13:49:32 +02:00 |
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Clifford Wolf
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6d69d4aaa8
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Added support for constant bit- or part-select for memory writes
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2014-07-17 13:13:21 +02:00 |
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Clifford Wolf
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543551b80a
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changes in verilog frontend for new $mem/$memwr WR_EN interface
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2014-07-16 12:49:50 +02:00 |
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Clifford Wolf
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55a1b8dbac
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Fixed processing of initial values for block-local variables
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2014-07-11 13:05:53 +02:00 |
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Clifford Wolf
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076182c34e
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Fixed handling of mixed real/int ternary expressions
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2014-06-25 10:05:36 +02:00 |
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Clifford Wolf
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4fc43d1932
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More found_real-related fixes to AstNode::detectSignWidthWorker
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2014-06-24 15:08:48 +02:00 |
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Clifford Wolf
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65b2e9c064
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fixed signdness detection for expressions with reals
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2014-06-21 21:41:13 +02:00 |
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Clifford Wolf
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80e4594695
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Added AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 21:39:25 +02:00 |
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Clifford Wolf
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798ff88855
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Improved handling of relational op of real values
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2014-06-17 12:47:51 +02:00 |
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Clifford Wolf
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6c17d4f242
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Improved ternary support for real values
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2014-06-16 15:12:24 +02:00 |
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Clifford Wolf
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82bbd2f077
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Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
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2014-06-16 15:05:37 +02:00 |
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Clifford Wolf
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5bfe865cec
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Added found_real feature to AstNode::detectSignWidth
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2014-06-16 15:00:57 +02:00 |
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Clifford Wolf
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4d1df128fa
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Improved AstNode::realAsConst for large numbers
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2014-06-15 09:27:09 +02:00 |
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Clifford Wolf
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48dc6ab98d
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Improved AstNode::asReal for large integers
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2014-06-15 08:38:31 +02:00 |
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Clifford Wolf
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149fe83a8d
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improved (fixed) conversion of real values to bit vectors
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2014-06-14 21:00:51 +02:00 |
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Clifford Wolf
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d5765b5e14
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Fixed relational operators for const real expressions
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2014-06-14 19:33:58 +02:00 |
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Clifford Wolf
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f3b4a9dd24
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Added support for math functions
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2014-06-14 13:36:23 +02:00 |
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Clifford Wolf
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9bd7d5c468
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Added handling of real-valued parameters/localparams
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2014-06-14 12:00:47 +02:00 |
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Clifford Wolf
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fc7b6d172a
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Implemented more real arithmetic
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2014-06-14 11:27:05 +02:00 |
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Clifford Wolf
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442a8e2875
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Implemented basic real arithmetic
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2014-06-14 08:51:22 +02:00 |
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Clifford Wolf
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9dd16fa41c
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Added real->int convertion in ast genrtlil
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2014-06-14 07:44:19 +02:00 |
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Clifford Wolf
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7ef0da32cd
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Added Verilog lexer and parser support for real values
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2014-06-13 11:29:23 +02:00 |
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Clifford Wolf
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e275e8eef9
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Add support for cell arrays
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2014-06-07 11:48:50 +02:00 |
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Clifford Wolf
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0b1ce63a19
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Added support for repeat stmt in const functions
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2014-06-07 10:47:53 +02:00 |
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Clifford Wolf
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7c8a7b2131
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further improved const function support
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2014-06-07 00:02:05 +02:00 |
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Clifford Wolf
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76da2fe172
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improved const function support
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2014-06-06 22:55:02 +02:00 |
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Clifford Wolf
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5c10d2ee36
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fix functions with no block (but single statement, loop, etc.)
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2014-06-06 21:29:23 +02:00 |
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Clifford Wolf
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ab54ce17c8
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improved ast simplify of const functions
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2014-06-06 17:40:45 +02:00 |
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Clifford Wolf
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b5cd7a0179
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added while and repeat support to verilog parser
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2014-06-06 17:40:04 +02:00 |
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Clifford Wolf
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09805ee9ec
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Include id2ast pointers when dumping AST
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2014-03-05 19:56:31 +01:00 |
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Clifford Wolf
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d6a01fe412
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Fixed merging of compatible wire decls in AST frontend
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2014-03-05 19:55:58 +01:00 |
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