Clifford Wolf
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f0c9a099d2
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Added "synth -nofsm"
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2015-07-02 15:25:38 +02:00 |
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Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
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Clifford Wolf
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053058d781
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Added opt_const -clkinv
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2015-07-01 10:49:21 +02:00 |
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Clifford Wolf
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ee9188a5b4
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Added logic-loop error handling to freduce
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2015-06-30 17:11:46 +02:00 |
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Clifford Wolf
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7987f23200
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-06-30 01:49:55 +02:00 |
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Clifford Wolf
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77e89399a6
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Bugfix in chparam
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2015-06-30 01:38:34 +02:00 |
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Clifford Wolf
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caa274ada6
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Added design->rename(module, new_name)
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2015-06-30 01:37:59 +02:00 |
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Clifford Wolf
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358e415918
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Added YosysJS.create_worker()
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2015-06-28 17:47:58 +02:00 |
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Clifford Wolf
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df0163cd2b
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iCE40: set min bram efficiency to 2%
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2015-06-20 09:31:19 +02:00 |
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Clifford Wolf
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94fbaff58f
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Using static mem size of 128 MB in emcc build
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2015-06-20 08:58:02 +02:00 |
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Clifford Wolf
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3123c45415
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Added init support to SMV back-end
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2015-06-19 16:43:02 +02:00 |
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Clifford Wolf
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6c6bf4999e
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Progress in SMV back-end
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2015-06-19 16:26:53 +02:00 |
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Clifford Wolf
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8c79765de5
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Progress in SMV back-end
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2015-06-19 14:08:46 +02:00 |
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Clifford Wolf
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8a86162ae9
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Progress in SMV back-end
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2015-06-18 16:29:11 +02:00 |
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Clifford Wolf
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8e84418225
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Progress in SMV back-end
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2015-06-17 09:56:42 +02:00 |
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Clifford Wolf
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99100f367d
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Added "rename -top new_name"
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2015-06-17 09:38:56 +02:00 |
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Clifford Wolf
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9f7a5b4ef9
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Progress in SMV back-end
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2015-06-17 07:24:27 +02:00 |
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Clifford Wolf
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b8c5e27006
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Progress in SMV back-end
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2015-06-16 19:05:26 +02:00 |
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Clifford Wolf
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ed128b82d7
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Added "synth -nordff -noalumacc"
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2015-06-15 17:07:40 +02:00 |
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Clifford Wolf
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52315039c5
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Progress in SMV back-end
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2015-06-15 17:01:01 +02:00 |
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Clifford Wolf
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0f01ef61ef
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Progress in SMV back-end
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2015-06-15 13:24:17 +02:00 |
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Clifford Wolf
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ea23bb8aa4
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Added "write_smv" skeleton
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2015-06-15 00:46:27 +02:00 |
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Clifford Wolf
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93685a77c6
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Removed debug code from write_smt2
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2015-06-14 16:22:06 +02:00 |
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Clifford Wolf
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66910e15b2
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Modernized memory_dff (and fixed a bug)
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2015-06-14 16:15:51 +02:00 |
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Clifford Wolf
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f6eca509bb
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Added "memory -nordff"
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2015-06-14 15:47:11 +02:00 |
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Clifford Wolf
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255dcb27a0
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Added write_smt2 -mem
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2015-06-14 15:46:47 +02:00 |
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Clifford Wolf
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285f140f60
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Makefile fix for YosysJS build
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2015-06-11 15:48:40 +02:00 |
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Clifford Wolf
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4c733301e6
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Fixed cstr_buf for std::string with small string optimization
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2015-06-11 13:39:49 +02:00 |
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Clifford Wolf
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3a6abc9bf6
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Improvements in cellaigs.cc and "json -aig"
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2015-06-11 10:48:16 +02:00 |
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Clifford Wolf
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1ae360cf72
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AigMaker refactoring
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2015-06-10 23:00:12 +02:00 |
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Clifford Wolf
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e534881794
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Added "json -aig"
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2015-06-10 08:13:56 +02:00 |
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Clifford Wolf
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56d4822719
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Renamed "aig" to "aigmap"
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2015-06-10 07:24:26 +02:00 |
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Clifford Wolf
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85287295b2
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Fixed cellaigs port extending
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2015-06-10 07:16:30 +02:00 |
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Clifford Wolf
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66f9ee412a
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Added "aig" pass
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2015-06-09 22:33:26 +02:00 |
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Clifford Wolf
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9500b564ac
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synth_ice40 now flattens by default
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2015-06-09 20:28:17 +02:00 |
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Clifford Wolf
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e49e2662aa
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Added cellaigs API
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2015-06-09 09:54:22 +02:00 |
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Clifford Wolf
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b57cb4a7fe
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Merge clock inverters in memory_dff
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2015-06-09 07:25:12 +02:00 |
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Clifford Wolf
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c88be7bae5
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Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys
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2015-06-09 06:42:07 +02:00 |
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luke whittlesey
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2f90499e3d
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$mem cell in verilog backend : grouped writes by clock
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2015-06-08 17:35:40 -04:00 |
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Clifford Wolf
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de4f4dad3c
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Fixed "avail_parameters" handling in module clone/copy
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2015-06-08 14:49:34 +02:00 |
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Clifford Wolf
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98650a0609
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Added log_dump() support for IdStrings
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2015-06-08 14:49:02 +02:00 |
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Clifford Wolf
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13983e8318
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Fixed handling of parameters with reversed range
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2015-06-08 14:03:06 +02:00 |
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luke whittlesey
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a8fe040906
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Bug fix in $mem verilog backend + changed tests/bram flow of make test.
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2015-06-04 16:12:40 -04:00 |
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Clifford Wolf
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08f9b38a9c
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Added opt_share -share_all
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2015-05-31 14:24:34 +02:00 |
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Clifford Wolf
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09ef279b60
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Added iCE40 PLL cells
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2015-05-31 13:10:43 +02:00 |
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Clifford Wolf
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522705cc28
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Added liberty dont_use support to dfflibmap
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2015-05-31 07:51:12 +02:00 |
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Clifford Wolf
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99b8746d27
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Fixed signedness of genvar expressions
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2015-05-29 20:08:00 +02:00 |
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Clifford Wolf
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c329233f0d
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Added output args to synth_ice40
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2015-05-26 17:08:53 +02:00 |
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Clifford Wolf
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08a4af3cde
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Improvements in BLIF front-end
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2015-05-24 08:03:21 +02:00 |
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Clifford Wolf
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313f570fcc
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improved ice40 SB_IO sim model
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2015-05-23 10:17:03 +02:00 |
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