stv0g/yosys
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity
%!d() commits 1 branch 6 tags 8.6 MiB
Commit graph

2 commits

Author SHA1 Message Date
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
5bf33de24a Added setattr and setparam commands 2014-02-05 11:11:55 +01:00