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  • c469be883b Improvements in tests/vloghtb Clifford Wolf 2014-07-28 09:15:40 +02:00
  • 8b0f50792c Added techmap -extern Clifford Wolf 2014-07-27 21:13:23 +02:00
  • c4bdba78cb Added proper Design->addModule interface Clifford Wolf 2014-07-27 21:12:09 +02:00
  • 5da343b7de Added topological sorting to techmap Clifford Wolf 2014-07-27 16:19:24 +02:00
  • 0c86d6106c Added SigPool::check(bit) Clifford Wolf 2014-07-27 15:38:02 +02:00
  • ddd31a0b66 Small improvements in PerformanceTimer API Clifford Wolf 2014-07-27 15:14:02 +02:00
  • 77a1462f2d Fixed bug in opt_clean Clifford Wolf 2014-07-27 15:13:29 +02:00
  • d07a871d35 Improved performance of opt_const on large modules Clifford Wolf 2014-07-27 14:50:25 +02:00
  • 4be645860b Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs Clifford Wolf 2014-07-27 14:47:48 +02:00
  • cbc3a46a97 Added RTLIL::SigSpecConstIterator Clifford Wolf 2014-07-27 14:47:23 +02:00
  • dbb3556e3f Fixed a bug in opt_clean and some RTLIL API usage cleanups Clifford Wolf 2014-07-27 13:19:05 +02:00
  • d878fcbdc7 Added log_cmd_error_expection Clifford Wolf 2014-07-27 12:04:12 +02:00
  • 7661ded8dd Fixed verific bindings for new RTLIL api Clifford Wolf 2014-07-27 12:00:28 +02:00
  • 6b34215efd Fixed ilang parser for new RTLIL API Clifford Wolf 2014-07-27 11:56:35 +02:00
  • 49f72421d5 Using new obj iterator API in a few places Clifford Wolf 2014-07-27 10:41:42 +02:00
  • 675cb93da9 Added RTLIL::Module::wire(id) and cell(id) lookup functions Clifford Wolf 2014-07-27 11:03:56 +02:00
  • 0bd8fafbd2 Added RTLIL::Design::modules() Clifford Wolf 2014-07-27 10:40:31 +02:00
  • 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ Clifford Wolf 2014-07-27 10:18:00 +02:00
  • d088854b47 Added conversion from ObjRange to std::vector and std::set Clifford Wolf 2014-07-27 10:41:06 +02:00
  • 1c8fdaeef8 Added RTLIL::ObjIterator and RTLIL::ObjRange Clifford Wolf 2014-07-27 10:13:22 +02:00
  • ddc5b41848 Using std::move() in SigSpec move constructor Clifford Wolf 2014-07-27 09:20:59 +02:00
  • 7f3dc86ecd Added RTLIL::SigSpec move constructor and move assignment operator Clifford Wolf 2014-07-27 02:11:57 +02:00
  • c91570bde3 Mostly cosmetic changes to rtlil.h Clifford Wolf 2014-07-27 02:00:04 +02:00
  • 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ Clifford Wolf 2014-07-27 01:51:45 +02:00
  • f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ Clifford Wolf 2014-07-27 01:49:51 +02:00
  • d7916a49af New message for completion of build Clifford Wolf 2014-07-26 21:34:19 +02:00
  • d68c993ed2 Changed more code to the new RTLIL::Wire constructors Clifford Wolf 2014-07-26 21:16:05 +02:00
  • 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors Clifford Wolf 2014-07-26 20:12:50 +02:00
  • d49dec1f86 Added tests/various/.gitignore Clifford Wolf 2014-07-26 17:43:41 +02:00
  • b21ebe1859 Added tests/various/submod_extract.ys Clifford Wolf 2014-07-26 17:22:18 +02:00
  • 267c615640 Added support for here documents Clifford Wolf 2014-07-26 17:21:40 +02:00
  • 3f4e3ca8ad More RTLIL::Cell API usage cleanups Clifford Wolf 2014-07-26 16:14:02 +02:00
  • 97a59851a6 Added RTLIL::Cell::has(portname) Clifford Wolf 2014-07-26 16:11:28 +02:00
  • a84cb04935 Merge automatic and manual code changes for new cell connections API Clifford Wolf 2014-07-26 16:00:30 +02:00
  • f8fdc47d33 Manual fixes for new cell connections API Clifford Wolf 2014-07-26 15:57:57 +02:00
  • b7dda72302 Changed users of cell->connections_ to the new API (sed command) Clifford Wolf 2014-07-26 14:32:50 +02:00
  • cd6574ecf6 Added some missing "const" in rtlil.h Clifford Wolf 2014-07-26 15:57:27 +02:00
  • 7ac9dc7f6e Added RTLIL::Module::connections() Clifford Wolf 2014-07-26 14:38:33 +02:00
  • b03aec6e32 Added RTLIL::Module::connect(const RTLIL::SigSig&) Clifford Wolf 2014-07-26 14:31:47 +02:00
  • 027819c7e8 Use "wget -N" in tests/vloghtb/run-test.sh Clifford Wolf 2014-07-26 14:08:43 +02:00
  • b90f443338 Added "passed" message to make test targets Clifford Wolf 2014-07-26 14:08:20 +02:00
  • 3719281ed4 Automatically pack SigSpec on copy/assign Clifford Wolf 2014-07-26 13:59:30 +02:00
  • e75e495c2b Added new RTLIL::Cell port access methods Clifford Wolf 2014-07-26 12:22:58 +02:00
  • cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ Clifford Wolf 2014-07-26 11:58:03 +02:00
  • 665759fcee Cosmetic fixes for "make abc" Clifford Wolf 2014-07-26 11:55:58 +02:00
  • f8a68b8f55 Added "Checklist for adding internal cell types" Clifford Wolf 2014-07-26 11:23:43 +02:00
  • 4755e14e7b Added copy-constructor-like module->addCell(name, other) method Clifford Wolf 2014-07-26 00:38:44 +02:00
  • 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells Clifford Wolf 2014-07-25 15:05:18 +02:00
  • 5826670009 Various RTLIL::SigSpec related code cleanups Clifford Wolf 2014-07-25 14:23:31 +02:00
  • c762050e7f Added RTLIL::SigSpec is_chunk()/as_chunk() API Clifford Wolf 2014-07-25 14:23:10 +02:00
  • 1834af5e53 Added "make vgtest" Clifford Wolf 2014-07-25 13:15:46 +02:00
  • 309d64d46a Fixed two memory leaks in ast simplify Clifford Wolf 2014-07-25 13:07:31 +02:00
  • 50f22ff30c Renamed some of the test cases in tests/simple to avoid name collisions Clifford Wolf 2014-07-25 13:01:45 +02:00
  • 0520bfea89 Fixed memory corruption in "opt_reduce" pass Clifford Wolf 2014-07-25 12:49:51 +02:00
  • c4e4f79a2a Disabled cover() for non-linux builds Clifford Wolf 2014-07-25 12:22:37 +02:00
  • a8706b73a2 Added more stuff to checklist Clifford Wolf 2014-07-25 12:16:23 +02:00
  • 1488bc0c4f Updated verific build/test instructions Clifford Wolf 2014-07-25 12:16:03 +02:00
  • 91bf0c90c8 Improvements in "cover" command Clifford Wolf 2014-07-25 12:04:40 +02:00
  • 6789e3002a Removed Minisat dependency on zlib Clifford Wolf 2014-07-25 03:31:16 +02:00
  • e4a0ab9bed Added more stuff to the checklist Clifford Wolf 2014-07-25 03:18:16 +02:00
  • 7f1789ad1b Fixed typo in cover id Clifford Wolf 2014-07-25 03:17:35 +02:00
  • cd69925437 Added "make clean-abc" Clifford Wolf 2014-07-25 03:17:06 +02:00
  • 01dbf12ac9 Further improved "make" prettiness Clifford Wolf 2014-07-25 03:12:14 +02:00
  • 6aa792c864 Replaced more old SigChunk programming patterns Clifford Wolf 2014-07-24 22:47:57 +02:00
  • 7a608437c6 Updated ABC to hg id "b1e63d18768d" Clifford Wolf 2014-07-24 20:57:21 +02:00
  • 9962384d3e Added cover() calls to opt_const Clifford Wolf 2014-07-24 19:36:43 +02:00
  • 10d2402e2f Added cover_list() API Clifford Wolf 2014-07-24 19:36:20 +02:00
  • 45b4154b37 Added "make SMALL=1" Clifford Wolf 2014-07-24 19:03:57 +02:00
  • 34ea9e3f09 Now "make PRETTY=1" is the default setting Clifford Wolf 2014-07-24 17:55:55 +02:00
  • 38afbe62ef Added percentage display to "make PRETTY=1" Clifford Wolf 2014-07-24 17:53:11 +02:00
  • b17d6531c8 Added "make PRETTY=1" Clifford Wolf 2014-07-24 17:15:01 +02:00
  • 2f54345cff Added "cover" command Clifford Wolf 2014-07-24 15:06:45 +02:00
  • e589289df7 Some improvements in SigSpec packing/unpacking and checking Clifford Wolf 2014-07-24 15:05:41 +02:00
  • 7679000673 Now using a dedicated ELF section for all coverage counters Clifford Wolf 2014-07-24 15:05:05 +02:00
  • 22ede43b3f Small changes regarding cover() and check() in SigSpec Clifford Wolf 2014-07-24 04:46:36 +02:00
  • 3a2c535777 Renamed RELEASE_CHECKLIST -> CHECKLIST Clifford Wolf 2014-07-24 04:24:47 +02:00
  • 798f713629 Added support for YOSYS_COVER_FILE env variable Clifford Wolf 2014-07-24 04:16:32 +02:00
  • 1b0d5fc22d Added cover() calls to RTLIL::SigSpec methods Clifford Wolf 2014-07-24 03:50:28 +02:00
  • 9cf12570ba Added support for YOSYS_COVER_DIR env variable Clifford Wolf 2014-07-24 03:49:32 +02:00
  • 6b1018314c Added cover() API Clifford Wolf 2014-07-24 03:48:38 +02:00
  • b31762d158 Added RELEASE_CHECKLIST Clifford Wolf 2014-07-24 02:13:37 +02:00
  • 2267db5834 Added "make config-gcc-4.7" Clifford Wolf 2014-07-24 02:12:24 +02:00
  • fa71ae89ac Added "make vloghtb" Clifford Wolf 2014-07-24 02:11:12 +02:00
  • 82fa356037 Added hashing to RTLIL::SigSpec relational and equal operators Clifford Wolf 2014-07-23 23:58:03 +02:00
  • f368d792fb Disabled RTLIL::SigSpec::check() in release builds Clifford Wolf 2014-07-23 21:42:44 +02:00
  • 95ac484548 Fixed release build Clifford Wolf 2014-07-23 21:38:18 +02:00
  • 375aa71dfe Various fixes in Verific frontend for new RTLIL API Clifford Wolf 2014-07-23 21:35:01 +02:00
  • 2a41afb7b2 Added RTLIL::SigSpec::repeat() Clifford Wolf 2014-07-23 21:34:14 +02:00
  • 20a7965f61 Various small fixes (from gcc compiler warnings) Clifford Wolf 2014-07-23 20:45:27 +02:00
  • c094c53de8 Removed RTLIL::SigSpec::optimize() Clifford Wolf 2014-07-23 20:32:28 +02:00
  • 8fd8e4a468 Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized Clifford Wolf 2014-07-23 20:11:55 +02:00
  • 3ec785b881 Fixed manual/CHAPTER_Prog/stubnets.cc Clifford Wolf 2014-07-23 19:36:43 +02:00
  • a62c21c9c6 Removed RTLIL::SigSpec::expand() method Clifford Wolf 2014-07-23 16:09:27 +02:00
  • 54552f6809 Added eclipse .setting folder to .gitignore Clifford Wolf 2014-07-23 19:30:21 +02:00
  • 4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it Clifford Wolf 2014-07-23 15:36:09 +02:00
  • 85db102e13 Replaced RTLIL::SigSpec::operator!=() with inline version Clifford Wolf 2014-07-23 15:35:09 +02:00
  • 5b51b67297 Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor Clifford Wolf 2014-07-23 10:05:42 +02:00
  • ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 Clifford Wolf 2014-07-23 09:48:26 +02:00
  • a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 Clifford Wolf 2014-07-23 08:40:31 +02:00
  • 260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 Clifford Wolf 2014-07-23 09:00:16 +02:00