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  • c61467a32c Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) Clifford Wolf 2014-07-23 08:59:54 +02:00
  • 115dd959d9 SigSpec refactoring: More cleanups of old SigSpec use pattern Clifford Wolf 2014-07-22 23:50:21 +02:00
  • 9e94f41b89 SigSpec refactoring: Added RTLIL::SigSpecIterator Clifford Wolf 2014-07-22 23:49:26 +02:00
  • 4a6d234ec7 SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands Clifford Wolf 2014-07-22 23:07:42 +02:00
  • 65a939cb27 Fixed memory corruption with new SigSpec API in proc_mux Clifford Wolf 2014-07-22 22:54:39 +02:00
  • f80da7b41d SigSpec refactoring: added RTLIL::SigSpec::operator[] Clifford Wolf 2014-07-22 22:54:03 +02:00
  • e7e30f1c86 fixed memory leak in fsm_opt Clifford Wolf 2014-07-22 22:52:57 +02:00
  • fd4cbe6275 SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form Clifford Wolf 2014-07-22 22:26:30 +02:00
  • a97be0828a Removed RTLIL::SigChunk::compare() Clifford Wolf 2014-07-22 21:40:52 +02:00
  • 08e1e25169 SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api Clifford Wolf 2014-07-22 21:33:52 +02:00
  • 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() Clifford Wolf 2014-07-22 20:58:44 +02:00
  • 7bffde6abd SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only Clifford Wolf 2014-07-22 20:39:13 +02:00
  • 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere Clifford Wolf 2014-07-22 20:15:14 +02:00
  • 16e5ae0b92 SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions Clifford Wolf 2014-07-22 20:12:15 +02:00
  • a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width Clifford Wolf 2014-07-22 19:56:17 +02:00
  • 3b5f4ff39c Fixed ilang parsing of process attributes Clifford Wolf 2014-07-22 20:35:58 +02:00
  • d6d0e08834 Fixed make rules for ilang parser Clifford Wolf 2014-07-22 20:18:05 +02:00
  • 0229d68fc9 Use "opt -fine" in test/vloght/test_mapopt.sh Clifford Wolf 2014-07-21 21:39:59 +02:00
  • 137dbf3cf7 Added "opt_const -keepdc" Clifford Wolf 2014-07-21 21:38:55 +02:00
  • 1873480ca5 Added mul to mux conversion to "opt_const -fine" Clifford Wolf 2014-07-21 17:19:50 +02:00
  • 1241a9fd50 Added "opt_const -fine" and "opt_reduce -fine" Clifford Wolf 2014-07-21 16:34:16 +02:00
  • 4147b55c23 Added "autoidx" statement to ilang file format Clifford Wolf 2014-07-21 15:15:18 +02:00
  • e035f1d886 Added opt_const support for simple identities Clifford Wolf 2014-07-21 14:09:11 +02:00
  • 668306d00f Various improvements in test/vloghtb Clifford Wolf 2014-07-21 14:08:13 +02:00
  • 550ac35873 Added support for scripts with labels Clifford Wolf 2014-07-21 13:28:12 +02:00
  • 361e0d62ff Replaced depricated NEW_WIRE macro with module->addWire() calls Clifford Wolf 2014-07-21 12:41:29 +02:00
  • 1d88f1cf9f Removed deprecated module->new_wire() Clifford Wolf 2014-07-21 12:35:06 +02:00
  • 3cb61d03f8 Wider range of cell types supported in "share" pass Clifford Wolf 2014-07-21 12:04:56 +02:00
  • c54d1f2ad1 Bugfix in satgen for cells with wider in- than outputs. Clifford Wolf 2014-07-21 12:03:41 +02:00
  • 54b0f2e659 Added module->remove(), module->addWire(), module->addCell(), cell->check() Clifford Wolf 2014-07-21 12:02:55 +02:00
  • caae6e19df Added log_ping() Clifford Wolf 2014-07-21 12:01:45 +02:00
  • b49beab1f3 Use ezSAT::non_incremental() in "share" pass Clifford Wolf 2014-07-21 02:08:38 +02:00
  • b1d520949b Added ezSAT::keep_cnf() and ezSAT::non_incremental() Clifford Wolf 2014-07-21 01:49:59 +02:00
  • ade659e617 Fixed ezSAT stand-alone build Clifford Wolf 2014-07-21 01:03:01 +02:00
  • 92c9403249 Updated minisat Clifford Wolf 2014-07-21 01:01:26 +02:00
  • c6b3f4e089 Using relative path names in minisat headers Clifford Wolf 2014-07-21 01:00:39 +02:00
  • 8836943693 Added yet another resource sharing test case Clifford Wolf 2014-07-20 20:45:01 +02:00
  • 04fcb07213 Added support for resource sharing in mux control logic Clifford Wolf 2014-07-20 20:44:14 +02:00
  • 1ce5e83555 Added "select -assert-count" Clifford Wolf 2014-07-20 20:15:49 +02:00
  • e9506bb2da Supercell creation for $div/$mod worked all along, fixed test benches Clifford Wolf 2014-07-20 18:54:06 +02:00
  • 7a6d578b81 Improved tests/share/generate.py Clifford Wolf 2014-07-20 17:06:57 +02:00
  • ff28029fdb Fixed creation of shift supercells in "share" pass Clifford Wolf 2014-07-20 17:06:36 +02:00
  • 4af8d84f01 Small fix in tests/vloghtb/run-test.sh Clifford Wolf 2014-07-20 17:05:20 +02:00
  • dd23e9a9db Activated tests/share in "make test" Clifford Wolf 2014-07-20 15:24:04 +02:00
  • 4c38ec1cc8 Added "miter -equiv -flatten" Clifford Wolf 2014-07-20 15:23:08 +02:00
  • 8d04ca7d22 Added call_on_selection() and call_on_module() API Clifford Wolf 2014-07-20 15:16:10 +02:00
  • 2e358bd667 Added tests/vloghtb/test_share.sh Clifford Wolf 2014-07-20 13:20:52 +02:00
  • 6f450d0224 Added tests/share for testing "share" supercell creation Clifford Wolf 2014-07-20 14:55:10 +02:00
  • 5b3ee7a072 Added "share" supercell creation Clifford Wolf 2014-07-20 15:00:18 +02:00
  • 7b98e46ac3 Added removing of always inactive cells to "share" pass Clifford Wolf 2014-07-20 11:41:57 +02:00
  • 8819493db4 Progress in "share" pass Clifford Wolf 2014-07-20 10:36:46 +02:00
  • e57db5e9b2 Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion Clifford Wolf 2014-07-20 11:00:09 +02:00
  • efa7884026 Added SIZE() macro Clifford Wolf 2014-07-20 10:36:14 +02:00
  • a6174aaf5e Added log_cell() Clifford Wolf 2014-07-20 10:35:47 +02:00
  • 15fd615da5 Progress in "share" pass Clifford Wolf 2014-07-20 03:03:04 +02:00
  • 3f9f0c047d Added tests/vloghtb Clifford Wolf 2014-07-20 02:19:44 +02:00
  • a30e2857c7 Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend Clifford Wolf 2014-07-20 02:16:30 +02:00
  • 0c67393313 Added support for $bu0 to verilog backend Clifford Wolf 2014-07-20 01:56:16 +02:00
  • 2278995bd8 Started to implement real resource sharing Clifford Wolf 2014-07-19 20:54:32 +02:00
  • 02f0acb3bc Fixed log_id() memory corruption Clifford Wolf 2014-07-19 20:53:29 +02:00
  • efd9604dfb Improved memory_share log messages Clifford Wolf 2014-07-19 15:46:11 +02:00
  • e0a819dbe5 More verbose memory_share help message Clifford Wolf 2014-07-19 15:34:14 +02:00
  • 297a0962ea Added SAT-based write-port sharing to memory_share Clifford Wolf 2014-07-19 15:33:55 +02:00
  • 35edac0b31 Added ModWalker helper class Clifford Wolf 2014-07-19 15:33:00 +02:00
  • 1c288adcc0 Some "const" cleanups in SigMap Clifford Wolf 2014-07-19 15:32:39 +02:00
  • 26f982ac0b Fixed bug in memory_share feedback-to-en code Clifford Wolf 2014-07-19 15:32:14 +02:00
  • e441f07d89 Added translation from read-feedback to en-signals in memory_share Clifford Wolf 2014-07-18 16:46:40 +02:00
  • 44f13aff92 Improved seeding of color rng in show command Clifford Wolf 2014-07-18 16:44:45 +02:00
  • a341931972 Only create collision detect logic in memory_share if necessary Clifford Wolf 2014-07-18 14:32:40 +02:00
  • ddb01df42e Bugfix in tests/memories/run-test.sh Clifford Wolf 2014-07-18 13:45:25 +02:00
  • 5d9127418b added tests/memories Clifford Wolf 2014-07-18 13:25:19 +02:00
  • ab4b26679f Added memory_share Clifford Wolf 2014-07-18 12:40:01 +02:00
  • a721f7d768 Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit> Clifford Wolf 2014-07-18 11:36:34 +02:00
  • 309ae98246 Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port Clifford Wolf 2014-07-18 10:28:45 +02:00
  • 2d69c309f9 Added function-like cell creation helpers Clifford Wolf 2014-07-18 10:27:06 +02:00
  • a8cedb2257 Added log_id() helper function Clifford Wolf 2014-07-18 10:26:01 +02:00
  • ec3a798194 Also simulate unmapped memories in "make test" Clifford Wolf 2014-07-17 16:53:52 +02:00
  • 9b183539af Implemented dynamic bit-/part-select for memory writes Clifford Wolf 2014-07-17 16:49:23 +02:00
  • f1ca93a0a3 Fixed simlib.v model for $mem Clifford Wolf 2014-07-17 16:48:36 +02:00
  • 5867f6bcdc Added support for bit/part select to mem2reg rewriter Clifford Wolf 2014-07-17 13:49:32 +02:00
  • 6d69d4aaa8 Added support for constant bit- or part-select for memory writes Clifford Wolf 2014-07-17 13:13:21 +02:00
  • 1b00861d0a Improved opt_reduce handling of mem wr_en mux bits Clifford Wolf 2014-07-17 12:12:04 +02:00
  • 274c514879 Fixed RTLIL::SigSpec::append_bit() for appending constants Clifford Wolf 2014-07-17 12:10:57 +02:00
  • b76bf05cda Added support for "blackbox" attribute to iopadmap Clifford Wolf 2014-07-17 08:59:07 +02:00
  • 64a6906cc4 Added support for "blackbox" attribute to flatten/techmap Clifford Wolf 2014-07-17 08:58:51 +02:00
  • b171a4c1bc Added "inout" ports support to read_liberty Clifford Wolf 2014-07-16 18:12:46 +02:00
  • 5057935722 Set blackbox attribute in "read_liberty -lib" Clifford Wolf 2014-07-16 18:12:16 +02:00
  • 24f58e57f3 Fixed spelling of "direction" in read_liberty messages Clifford Wolf 2014-07-16 18:02:28 +02:00
  • 02346cd1d5 Merged new $mem/$memwr WR_EN interface Clifford Wolf 2014-07-16 14:15:33 +02:00
  • 73a345294a Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface Clifford Wolf 2014-07-16 13:46:27 +02:00
  • d678b6533d improved opt_reduce for $mem/$memwr WR_EN multiplexers Clifford Wolf 2014-07-16 13:37:41 +02:00
  • 543551b80a changes in verilog frontend for new $mem/$memwr WR_EN interface Clifford Wolf 2014-07-16 12:23:47 +02:00
  • 765f172211 Changes to "memory" pass for new $memwr/$mem WR_EN interface Clifford Wolf 2014-07-16 12:13:13 +02:00
  • dcdd5c11b4 Updated simlib to new $mem/$memwr interface Clifford Wolf 2014-07-16 11:46:40 +02:00
  • 73e0e13d2f Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal Clifford Wolf 2014-07-16 11:38:02 +02:00
  • 964a67ac41 Added note to "make test": use git checkout of iverilog Clifford Wolf 2014-07-16 10:03:07 +02:00
  • 0f9ca49dc6 Added passing of various options to vhdl2verilog Clifford Wolf 2014-07-12 10:02:39 +02:00
  • 847e2ee4a1 Use "verilog -sv" to parse .sv files Clifford Wolf 2014-07-11 13:10:51 +02:00
  • 55a1b8dbac Fixed processing of initial values for block-local variables Clifford Wolf 2014-07-11 13:05:53 +02:00
  • 3b52121d32 now ignore init attributes on non-register wires in sat command Clifford Wolf 2014-07-05 11:17:40 +02:00