stv0g/yosys
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

Commit graph

  • 23f0a12c72 ezSAT bugfix: don't call virtual methods in base class constructor Clifford Wolf 2014-03-01 20:59:00 +01:00
  • edc2146056 Removed ezSAT::assumed() API Clifford Wolf 2014-03-01 20:55:06 +01:00
  • e3debea4e6 Removed ezSAT built-in brute-froce solver Clifford Wolf 2014-03-01 20:53:09 +01:00
  • ef90236a5d Fixed vhdl2verilog temp dir name Clifford Wolf 2014-03-01 17:48:15 +01:00
  • 04999f4af0 Fixed vhdl2verilog help message Clifford Wolf 2014-03-01 17:47:19 +01:00
  • 9e99984336 Fixed const folding of $bu0 cells Clifford Wolf 2014-02-27 04:09:32 +01:00
  • ae5032af84 Fixed bit-extending in $mux argument (use $bu0 instead of $pos) Clifford Wolf 2014-02-26 21:32:19 +01:00
  • aaaa604853 Added support for $bu0 to SatGen Clifford Wolf 2014-02-26 21:31:34 +01:00
  • 6bc94b7eb2 Don't blow up constants unneccessarily in Verilog frontend Clifford Wolf 2014-02-24 12:41:25 +01:00
  • dab1612f81 Added support for Minisat::SimpSolver + ezSAT frezze() API Clifford Wolf 2014-02-23 01:35:59 +01:00
  • b76528d8a5 Fixed small memory leak in Pass::call() Clifford Wolf 2014-02-23 01:28:29 +01:00
  • f8c9143b2b Fixed bug in generation of undefs for $memwr MUXes Clifford Wolf 2014-02-22 17:08:00 +01:00
  • 548519875b Fixed bug (typo) in passes/opt/opt_const.cc Clifford Wolf 2014-02-22 17:07:22 +01:00
  • 337b461d26 Added $lut support to blif backend (by user eddiehung from reddit) Clifford Wolf 2014-02-22 14:25:32 +01:00
  • 357f3f6e93 Added ezMiniSat EZMINISAT_INCREMENTAL compile-time option Clifford Wolf 2014-02-22 11:34:31 +01:00
  • 1ec01d8c63 Made MiniSat solver backend configurable in ezminisat.h Clifford Wolf 2014-02-22 01:29:02 +01:00
  • 8b508dc90b Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst Clifford Wolf 2014-02-21 23:34:45 +01:00
  • 0a60f95224 Added vhdl2verilog Clifford Wolf 2014-02-21 18:59:49 +01:00
  • 79edcd4318 Progress in presentation Clifford Wolf 2014-02-21 14:59:59 +01:00
  • 038eac7414 Better handling of nameDef and nameRef in edif backend Clifford Wolf 2014-02-21 13:40:43 +01:00
  • f3ff29d410 Fixed instantiating multi-bit ports in edif backend Clifford Wolf 2014-02-21 13:10:36 +01:00
  • 3c5e973092 Use private namespace in mem_simple_4x1_map Clifford Wolf 2014-02-21 12:14:38 +01:00
  • 81b3f52519 Added tests/techmap/mem_simple_4x1 Clifford Wolf 2014-02-21 12:06:40 +01:00
  • 79f8944811 Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param Clifford Wolf 2014-02-21 10:40:15 +01:00
  • 2aff7b2a47 Progress in presentation Clifford Wolf 2014-02-21 02:13:02 +01:00
  • 9351e4d3ca Progress in presentation Clifford Wolf 2014-02-20 23:44:28 +01:00
  • 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap Clifford Wolf 2014-02-20 23:42:07 +01:00
  • 737b71c735 Added "extract -ignore_parameters" and "extract -ignore_param ..." Clifford Wolf 2014-02-20 23:31:13 +01:00
  • 236fc4209c Added "extract -map %<design_name>" Clifford Wolf 2014-02-20 23:30:15 +01:00
  • 483c99fe46 Added "design -push" and "design -pop" Clifford Wolf 2014-02-20 23:28:59 +01:00
  • b0e84802ec Progress in presentation Clifford Wolf 2014-02-20 20:44:41 +01:00
  • 0dadfed46d Added connwrappers command Clifford Wolf 2014-02-20 20:44:11 +01:00
  • 4bd25edcd4 Cleanups in handling of read_verilog -defer and -icells Clifford Wolf 2014-02-20 19:12:32 +01:00
  • 98940260e1 Progress in presentation Clifford Wolf 2014-02-20 12:46:29 +01:00
  • 772330608a Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...) Clifford Wolf 2014-02-19 12:40:49 +01:00
  • 23a3b488a0 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-02-18 20:05:53 +01:00
  • 3d9da919d8 Progress in presentation Clifford Wolf 2014-02-18 19:37:39 +01:00
  • a71d09421d Added techmap support for _TECHMAP_CONNMAP_*_ Clifford Wolf 2014-02-18 19:23:32 +01:00
  • a78bba1f5c Added "sat -dump_cnf" Clifford Wolf 2014-02-18 09:29:08 +01:00
  • 32af10fa9b Coding style corrections in SatHelper::dump_model_to_vcd() Clifford Wolf 2014-02-18 09:28:05 +01:00
  • 61a2bf57b4 Improved non-verbose ezSAT::printDIMACS() format Clifford Wolf 2014-02-18 09:25:41 +01:00
  • 13051e6acf Added "sat -initsteps" Clifford Wolf 2014-02-18 09:03:16 +01:00
  • 02e6f2c5be Added Verilog support for "`default_nettype none" Clifford Wolf 2014-02-17 14:28:52 +01:00
  • 0851c2b6ea Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups Clifford Wolf 2014-02-17 13:57:14 +01:00
  • 4a948d780a Added "-dump_fail_to_vcd" argument to SAT solver Andrew Zonenberg 2014-02-17 06:06:04 -05:00
  • 0fbc1a59dd Progress in presentation Clifford Wolf 2014-02-17 09:45:04 +01:00
  • ca53ef5098 Better preserve wires when flattening (in comparison to techmap) Clifford Wolf 2014-02-17 09:44:39 +01:00
  • 37cbb1ca60 Progress in presentation Clifford Wolf 2014-02-16 22:31:53 +01:00
  • 6d63f39eb6 Added some additional checks to techmap Clifford Wolf 2014-02-16 22:18:06 +01:00
  • a9b11d7c83 Added CONSTMSK and CONSTVAL feature to techmap Clifford Wolf 2014-02-16 21:58:59 +01:00
  • 28e14ee50a Fixed handling of "keep" attribute on wires in opt_clean Clifford Wolf 2014-02-16 21:58:27 +01:00
  • 7d7e068dd1 Added a warning note about error reporting to read_verilog help message Clifford Wolf 2014-02-16 20:20:25 +01:00
  • f08c71b96c Progress in presentation Clifford Wolf 2014-02-16 17:56:19 +01:00
  • 42ce3db983 Fixed use of selection in splitnets command Clifford Wolf 2014-02-16 17:39:50 +01:00
  • d3dc22a90f Added recursion support to techmap Clifford Wolf 2014-02-16 17:16:44 +01:00
  • aeb36b0b8b Progress in presentation Clifford Wolf 2014-02-16 14:32:56 +01:00
  • 9c29969bbc Progress in presentation Clifford Wolf 2014-02-16 13:45:47 +01:00
  • 7ac524e8e8 Improved support for constant functions Clifford Wolf 2014-02-16 13:16:38 +01:00
  • b0ae19fa92 Now we are in Yoys 0.2.0+ development Clifford Wolf 2014-02-16 00:54:41 +01:00
  • c05c3098f1 Tagging Yoys 0.2.0 yosys-0.2.0 Clifford Wolf 2014-02-16 00:35:53 +01:00
  • 9a816b65a8 Added != support for relational select pattern Clifford Wolf 2014-02-16 00:16:54 +01:00
  • 623a68f528 Added iopadmap -bits Clifford Wolf 2014-02-15 21:59:26 +01:00
  • 118517ca5a Added ff and latch support to read_liberty Clifford Wolf 2014-02-15 19:36:33 +01:00
  • 96b1ebc8dc Bugfix in expression parser of read_liberty Clifford Wolf 2014-02-15 19:36:09 +01:00
  • cdf0f10760 Fixed dfflibmap for cell libraries with no set-reset-ff Clifford Wolf 2014-02-15 16:34:12 +01:00
  • 5e39e6ece2 Correctly convert constants to RTLIL (fixed undef handling) Clifford Wolf 2014-02-15 15:42:10 +01:00
  • 30379ea20d Added frontend (-f) option to autotest.sh Clifford Wolf 2014-02-15 15:40:17 +01:00
  • 67effc9f5b Fixed opt_const handling of double invert with non-1 output width Clifford Wolf 2014-02-15 13:16:08 +01:00
  • 4440610d3f Added liberty frontend Clifford Wolf 2014-02-15 12:57:28 +01:00
  • 45d2b6ffce Be more conservative with new const-function code Clifford Wolf 2014-02-14 20:45:30 +01:00
  • e8af3def7f Added support for FOR loops in function calls in parameters Clifford Wolf 2014-02-14 20:33:22 +01:00
  • 534c1a5dd0 Created basic support for function calls in parameter values Clifford Wolf 2014-02-14 19:56:44 +01:00
  • 3121d19d95 Added abc -keepff option Clifford Wolf 2014-02-14 11:28:42 +01:00
  • de3ea9269a updated default ABC command strings Clifford Wolf 2014-02-13 19:14:15 +01:00
  • a123941618 Updated ABC Clifford Wolf 2014-02-13 18:56:36 +01:00
  • cd9e8741a7 Implemented read_verilog -defer Clifford Wolf 2014-02-13 13:59:13 +01:00
  • b463907890 Removed double blanks in ABC default command sequences Clifford Wolf 2014-02-13 08:12:52 +01:00
  • c6236c9e97 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-02-13 08:09:17 +01:00
  • 7664f5d92b Updated ABC and some related changes Clifford Wolf 2014-02-13 08:07:08 +01:00
  • 6b210d2b6f Merge pull request #26 from ahmedirfan1983/btor Clifford Wolf 2014-02-12 23:46:58 +01:00
  • 08caa631dd Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-02-12 23:30:02 +01:00
  • 007bdff55d Added support for functions returning integer Clifford Wolf 2014-02-12 23:29:54 +01:00
  • ac896c63e2 modified btor synthesis script for correct use of splice command. Ahmed Irfan 2014-02-12 13:38:28 +01:00
  • 9ce7b0fc3b Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC) Clifford Wolf 2014-02-12 13:11:58 +01:00
  • ab71bd0746 Updated ABC to rev e97a6e1d59b9 Clifford Wolf 2014-02-12 08:35:42 +01:00
  • 0defc86519 renamed ilang "scope error" to "ilang error" Clifford Wolf 2014-02-11 19:17:07 +01:00
  • 45e468114a disabling splice command in the script Ahmed Irfan 2014-02-11 15:43:03 +01:00
  • 1d64b3e008 register output corrected Ahmed Irfan 2014-02-11 13:28:05 +01:00
  • 1a2dc48c2a Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor Ahmed Irfan 2014-02-11 13:26:43 +01:00
  • e8f6b8f201 added concat and slice cell translation Ahmed Irfan 2014-02-11 13:06:01 +01:00
  • d2fd45949d More Makefile cleanups Clifford Wolf 2014-02-11 12:58:08 +01:00
  • 4bd2d47e45 Improved "make manual" and "make clean" Clifford Wolf 2014-02-11 12:55:58 +01:00
  • fb186e6299 Improved ilang parser error messages Clifford Wolf 2014-02-09 15:35:31 +01:00
  • d229324420 fixed a bug in subcircuit library with cells that have connections to itself Clifford Wolf 2014-02-09 15:27:58 +01:00
  • 38469e7686 Various improvements in expose command (added -sep and -cut) Clifford Wolf 2014-02-09 11:07:46 +01:00
  • b6f33576d5 Added delete {-input|-output|-port} Clifford Wolf 2014-02-09 10:03:26 +01:00
  • b3b5fac191 Bugfix in delete command Clifford Wolf 2014-02-09 09:34:58 +01:00
  • 039bb456cc Added test cases for expose -evert-dff Clifford Wolf 2014-02-08 21:27:04 +01:00
  • 85914c36e5 Fixed handling of async reset in expose -evert-dff Clifford Wolf 2014-02-08 21:26:40 +01:00
  • db86aaa07d Build fixes for log cmd Clifford Wolf 2014-02-08 21:21:51 +01:00