yosys

stv0g/yosys

Fork 0

Commit graph

ed4bcd52e5 Fixed sign handling in constants Clifford Wolf 2013-11-07 14:53:10 +01:00
83a8b8b5ca Fixed const folding in corner cases with parameters Clifford Wolf 2013-11-07 14:08:53 +01:00
90300cbacc Removed done or obsolete TODO items Clifford Wolf 2013-11-07 12:55:09 +01:00
b52bf379b9 Fixed width detection for replicate operator Clifford Wolf 2013-11-07 12:43:04 +01:00
db42a8f89b Fixed $eq/$ne bitwise optimization in opt_const Clifford Wolf 2013-11-07 11:54:59 +01:00
536621a98b Fixed at_zero evaluation of dynamic ranges Clifford Wolf 2013-11-07 11:25:19 +01:00
f050c40519 Various fixes for correct parameter support Clifford Wolf 2013-11-07 09:58:15 +01:00
160adccca2 Fixed the fix for propagation of width hints for $signed() and $unsigned() Clifford Wolf 2013-11-07 03:01:28 +01:00
404b46674b Fixed techmap of $reduce_xnor with multi-bit outputs Clifford Wolf 2013-11-07 00:58:06 +01:00
b41740060b Fixed techmap of $gt and $ge with multi-bit outputs Clifford Wolf 2013-11-06 22:59:45 +01:00
f485962c5e Added handling of unconnected/unspecified signals to eval -vloghammer_report Clifford Wolf 2013-11-06 22:42:07 +01:00
7fe13faefa Fixed propagation of width hints for $signed() and $unsigned() Clifford Wolf 2013-11-06 22:41:21 +01:00
8c523ef81d Improved undef handling in == and != for ConstEval Clifford Wolf 2013-11-06 22:21:58 +01:00
baeca48a24 Additional fixes for undef propagation in concat and replicate ops Clifford Wolf 2013-11-06 21:16:54 +01:00
6fcbc79b5c Improved width extension with regard to undef propagation Clifford Wolf 2013-11-06 20:50:53 +01:00
f839b842a2 Fixed handling of undef values in POS cells in ConstEval Clifford Wolf 2013-11-06 18:45:31 +01:00
204572d926 Fixed handling of undef values in MUX select input in ConstEval Clifford Wolf 2013-11-06 14:12:44 +01:00
031a91dc94 Added correct RTL undef handling to eval vloghammer mode Clifford Wolf 2013-11-06 13:16:47 +01:00
f94266bb42 Added eval -vloghammer_report mode Clifford Wolf 2013-11-06 04:14:56 +01:00
1d34fd7608 Added support for "keep" attributes on wires Clifford Wolf 2013-11-05 15:52:29 +01:00
27fec4e77c Fixed sign handling in const eval of sshl and sshr Clifford Wolf 2013-11-05 10:22:22 +01:00
2b5f4d1df3 Makefile DESTDIR default (/usr/local) without quotes Clifford Wolf 2013-11-04 21:30:57 +01:00
f2786df146 Another fix for early width and sign detection in ast simplifier Clifford Wolf 2013-11-04 21:29:36 +01:00
31ddf7b9d4 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-11-04 16:51:13 +01:00
d38c67f53d Fixed const folding of ternary operator Clifford Wolf 2013-11-04 16:46:14 +01:00
8d226da694 Use proper bit width ans sign extension for const folding Clifford Wolf 2013-11-04 15:37:09 +01:00
f830666ec0 Merge pull request #16 from mschmoelzer/master Clifford Wolf 2013-11-04 04:35:35 -08:00
58cfce6c5a Allow setting of installation destination via DESTDIR variable in Makefile Martin Schmölzer 2013-11-04 11:15:15 +01:00
ba305a7ca6 Improved comments on topological sort in edif backend Clifford Wolf 2013-11-04 08:34:15 +01:00
1325514d33 Fixes for early width and sign detection in ast simplifier Clifford Wolf 2013-11-04 08:28:13 +01:00
472117d532 further improved early width and sign detection in ast simplifier Clifford Wolf 2013-11-04 06:04:42 +01:00
cd0fe7d786 Added simple topological sort to edif backend Clifford Wolf 2013-11-03 22:01:32 +01:00
1dcb683fcb Write yosys version to output files Clifford Wolf 2013-11-03 21:41:39 +01:00
eab536a203 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-11-03 21:13:21 +01:00
d2b083f5cb Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT Clifford Wolf 2013-11-03 18:56:45 +01:00
f7f0af6f9c Added resolution of positional arguments to hierarchy pass Clifford Wolf 2013-11-03 09:42:51 +01:00
4a60e5842d Ignore explicit unconnected ports in intersynth backend Clifford Wolf 2013-11-03 09:00:51 +01:00
ada80545fa Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes) Clifford Wolf 2013-11-02 21:13:01 +01:00
f912e029de Added roadmap to readme file Clifford Wolf 2013-11-02 13:19:04 +01:00
943329c1dc Various ast changes for early expression width detection (prep for constfold fixes) Clifford Wolf 2013-11-02 13:00:17 +01:00
0b4a64ac6a Added DFFSR cell to techlibs/cmos/cmos_cells.lib Clifford Wolf 2013-10-31 12:27:35 +01:00
0efe16f118 Added placeholder check to dfflibmap and cleaned up some other placeholder checks Clifford Wolf 2013-10-31 12:27:07 +01:00
961eaa0077 Changed MiniSAT feater defines again Clifford Wolf 2013-10-31 12:02:18 +01:00
d78a9dfb37 Added paragraph to README file to avoid mycells.lib confusion Clifford Wolf 2013-10-31 11:15:00 +01:00
f024b19ed9 README file typo fix Clifford Wolf 2013-10-31 01:15:07 +01:00
cc7986a3e5 Some additions to the README file Clifford Wolf 2013-10-31 01:09:24 +01:00
3fc6c9aac6 Fixed ezminisat C++ errors: undef PRIi64 Clifford Wolf 2013-10-30 17:25:39 +01:00
b8bfa020fa Added detection for endless recursion in fsm_detect pass Clifford Wolf 2013-10-30 00:47:58 +01:00
888c43210b Fixed help message typo (memory pass) Clifford Wolf 2013-10-30 00:47:31 +01:00
613750155d Added -format option to splitnets Clifford Wolf 2013-10-29 11:01:04 +01:00
6bfeb17f05 Merge pull request #12 from jameswalmsley/master Clifford Wolf 2013-10-27 14:35:15 -07:00
40b3551b45 [EXAMPLES] Ported the mojo counter example to Zynq ZED board. James Walmsley 2013-10-27 21:48:39 +01:00
f39c0c9928 Fixed get_share_file_name() for installed yosys Clifford Wolf 2013-10-27 10:05:19 +01:00
88cd2eadf5 Cleanups in xilinx examples Clifford Wolf 2013-10-27 09:52:00 +01:00
4a3669d871 Added synth_xilinx command Clifford Wolf 2013-10-27 09:33:47 +01:00
73e68fe323 Added API and Makefile rules for share/ files Clifford Wolf 2013-10-27 09:33:26 +01:00
bd2c8ec886 Added design->full_selection() helper method Clifford Wolf 2013-10-27 09:30:58 +01:00
90b016716b Moved simple xilinx counter sim example to subdir Clifford Wolf 2013-10-27 09:30:17 +01:00
02f321b6fc Xilinx mojo_counter example is now working Clifford Wolf 2013-10-27 08:21:56 +01:00
d9fa1e5a1d Fixed hex string generation bug in edif backend Clifford Wolf 2013-10-27 08:21:05 +01:00
d635f8adaa Renamed techlibs/xilinx7 to techlibs/xilinx Clifford Wolf 2013-10-26 22:29:40 +02:00
4007b41d40 Improved xilinx mojo_counter example Clifford Wolf 2013-10-26 22:28:42 +02:00
ceb971eab9 Added support for i/o buffers to iopadmap Clifford Wolf 2013-10-26 22:27:40 +02:00
b934a2d209 Added another xilinx example (not funcional yet) Clifford Wolf 2013-10-26 17:22:29 +02:00
dd56004fc0 Added support for sr flip-flops to dfflibmap Clifford Wolf 2013-10-24 18:20:06 +02:00
628b994cf6 Added support for complex set-reset flip-flops in proc_dff Clifford Wolf 2013-10-24 16:54:05 +02:00
e679a5d046 Fixed handling of boolean attributes (passes) Clifford Wolf 2013-10-24 11:37:54 +02:00
e9dede01ca Fixed handling of boolean attributes (backends) Clifford Wolf 2013-10-24 11:27:30 +02:00
23cf23418c Fixed handling of boolean attributes (frontends) Clifford Wolf 2013-10-24 11:20:13 +02:00
eae43e2db4 Fixed handling of boolean attributes (kernel) Clifford Wolf 2013-10-24 10:59:27 +02:00
77726fb5fe Fixed parsing of value-less attributes in ilang Clifford Wolf 2013-10-23 18:38:31 +02:00
d61699843f Improved handling of dff with async resets Clifford Wolf 2013-10-21 14:51:58 +02:00
56ea230676 Added handling of multiple async paths in proc_arst Clifford Wolf 2013-10-19 00:50:13 +02:00
8e8f1994b8 Changed NEW_WIRE API to return the wire, not the signal Clifford Wolf 2013-10-18 14:19:45 +02:00
bfa1a65fa9 Added dffsr support to proc_dff pass Clifford Wolf 2013-10-18 13:26:52 +02:00
cc5e379eca Added RTLIL NEW_WIRE macro Clifford Wolf 2013-10-18 13:25:24 +02:00
0836a1f2ba Bugfix in dffsr techmap rules Clifford Wolf 2013-10-18 13:24:44 +02:00
8197169f8d Added techmap rules for $sr, $dffsr and $dlatch Clifford Wolf 2013-10-18 12:29:21 +02:00
e0f693cbb0 Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ Clifford Wolf 2013-10-18 12:13:34 +02:00
5998c101a4 Added $sr, $dffsr and $dlatch cell types Clifford Wolf 2013-10-18 11:56:16 +02:00
9bc703b964 Improved way of connecting ports in techmap pass Clifford Wolf 2013-10-17 22:19:38 +02:00
8cc53ef72c Only prefer connected signals iff they have public names Clifford Wolf 2013-10-17 22:10:55 +02:00
30b0de006f Added -buf, -true and -false options to blif backend Clifford Wolf 2013-10-17 21:37:18 +02:00
95dbacefbf Fixed bug in synthesis of memories that are never written Clifford Wolf 2013-10-17 21:00:37 +02:00
c20571ca5e Avoid re-arranging signals on register outputs Clifford Wolf 2013-10-17 20:48:40 +02:00
f5c0ed6c79 Fixed detection of major wires in opt_clean Clifford Wolf 2013-10-17 02:41:59 +02:00
96e7abad48 Added iopadmap pass Clifford Wolf 2013-10-16 16:16:06 +02:00
b6db2d9b33 Moved dfflibmap from passes/dfflibmap to passes/techmap Clifford Wolf 2013-10-16 15:32:26 +02:00
5745d3de9a Added map, par and bitgen to xlinx7 example Clifford Wolf 2013-10-16 10:57:18 +02:00
845590aa8e Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";' Patch by Tim Edwards Clifford Wolf 2013-10-16 06:32:35 +02:00
a12d39bc86 Added recommended apt-get commands to README Clifford Wolf 2013-10-11 22:25:23 +02:00
a97520785a Fixed minisat include Clifford Wolf 2013-10-11 21:17:01 +02:00
02efafa7f1 Pinned ABC revision to 0f9e5488ced3 Clifford Wolf 2013-10-03 16:03:30 +02:00
5dce6379aa Improvements in EDIF backend Clifford Wolf 2013-09-17 13:07:12 +02:00
dc767d4e4c Added additional options to BLIF backend Clifford Wolf 2013-09-15 13:33:33 +02:00
0ec5542ab4 Added BLIF backend Clifford Wolf 2013-09-15 13:13:01 +02:00
28069e8a10 A couple of small fixes in SPICE backend Clifford Wolf 2013-09-15 12:19:06 +02:00
288ba9618a Moved common techlib files to techlibs/common Clifford Wolf 2013-09-15 11:52:57 +02:00
647c23b7b7 Updated manual Clifford Wolf 2013-09-15 11:41:05 +02:00
2c9bd23801 Added spice testbench to techlibs/cmos Clifford Wolf 2013-09-14 13:29:11 +02:00