yosys

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bbe5aa446b Added spice backend Clifford Wolf 2013-09-14 11:23:45 +02:00
70476e2431 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-09-03 19:10:25 +02:00
73914d1a41 Added -selected option to various backends Clifford Wolf 2013-09-03 19:10:11 +02:00
09e200797a Encode large (>32 bits) parameters as hex string in edif backend Clifford Wolf 2013-08-28 08:48:49 +02:00
2feee7415d Improved edif backend Clifford Wolf 2013-08-27 14:22:11 +02:00
6685ad436e Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos) Clifford Wolf 2013-08-27 13:12:26 +02:00
5059b31660 Added simple xilinx7 technology mapping files Clifford Wolf 2013-08-22 20:26:19 +02:00
39ee561169 More explicit integer output in verilog backend Clifford Wolf 2013-08-22 20:22:19 +02:00
4f4cb2307f Added correct encoding of identifiers in EDIF backend Clifford Wolf 2013-08-22 14:30:33 +02:00
aba8639a3f Added edif backend (still under construction) Clifford Wolf 2013-08-22 11:34:55 +02:00
8409956c0c Merge pull request #10 from hansiglaser/master Clifford Wolf 2013-08-21 09:47:06 -07:00
f8107ab7fc Some minor documentation fixes Clifford Wolf 2013-08-21 12:16:44 +02:00
f352205635 fixed Verilog parser filename and line numbering issue with include files Johann Glaser 2013-08-21 09:20:59 +02:00
459e8964fd Merge pull request #9 from hansiglaser/master Clifford Wolf 2013-08-20 09:38:31 -07:00
a99c224157 Added support for include directories with the new '-I' argument of the 'read_verilog' command Johann Glaser 2013-08-20 15:48:16 +02:00
8e31a92407 Merge pull request #8 from hansiglaser/master Clifford Wolf 2013-08-20 03:36:34 -07:00
6c4cbc03c2 Added support for notif0/notif1 primitives Johann Glaser 2013-08-20 11:23:59 +02:00
e3aa0514f2 Added cleaning of old version_* files to version_* make rule Clifford Wolf 2013-08-20 10:12:54 +02:00
485e870bcd Added version info to yosys command and added -V option Clifford Wolf 2013-08-20 09:48:12 +02:00
1af1cebb64 Minor fixes in abc build instructions and abc pass Clifford Wolf 2013-08-20 09:46:05 +02:00
0003743432 Fixed width and sign detection for ** operator Clifford Wolf 2013-08-19 20:58:01 +02:00
8656b1c08f Added support for bufif0/bufif1 primitives Clifford Wolf 2013-08-19 19:50:04 +02:00
4214561890 Improved ast dumping (ast/verilog frontend) Clifford Wolf 2013-08-19 19:49:14 +02:00
a860efa8ac Implemented same div-by-zero behavior as found in other synthesis tools Clifford Wolf 2013-08-15 21:00:06 +02:00
78658199e6 Fixed signed div/mod in const eval (rounding and stuff) Clifford Wolf 2013-08-15 18:23:42 +02:00
457dc09cdc Added ezsat api for creation of anonymous vectors Clifford Wolf 2013-08-15 14:40:26 +02:00
2f3da54f26 Added sat -ignore_div_by_zero switch Clifford Wolf 2013-08-15 11:40:01 +02:00
d0e93e04d1 Added eval -brute_force_equiv_checker_x mode Clifford Wolf 2013-08-15 11:09:30 +02:00
759852914d Added support for "2**n" shifter encoding Clifford Wolf 2013-08-12 14:47:50 +02:00
ccf36cb7d8 Added SAT support for $div and $mod cells Clifford Wolf 2013-08-11 16:27:15 +02:00
a5836af172 Added "clean -purge" and ";;;" support Clifford Wolf 2013-08-11 13:59:14 +02:00
080f0aac34 Added ";;" as shortcut for "; clean;" Clifford Wolf 2013-08-11 13:33:38 +02:00
6068b8902f freduce performance fix Clifford Wolf 2013-08-10 15:03:13 +02:00
c8763301b4 Added $div and $mod technology mapping Clifford Wolf 2013-08-09 17:09:24 +02:00
376150c926 Added techmap -opt mode Clifford Wolf 2013-08-09 15:20:22 +02:00
05483619f0 Some fixes to improve determinism Clifford Wolf 2013-08-09 12:42:32 +02:00
d97782b848 Sort ctrl signals in fsm_extract Clifford Wolf 2013-08-08 15:46:00 +02:00
6a40e46a04 Added -try option to freduce pass Clifford Wolf 2013-08-08 10:56:27 +02:00
8cd153612e Added "clean" command (less verbose opt_clean) Clifford Wolf 2013-08-08 10:53:37 +02:00
56e01ce389 Fixed topological ordering in freduce pass Clifford Wolf 2013-08-07 19:38:19 +02:00
e729857647 Improved handling of private names in opt_clean and rename commands Clifford Wolf 2013-08-07 18:39:49 +02:00
3f5d7df603 Added stubnets example to manual prog chapter Clifford Wolf 2013-08-07 02:19:35 +02:00
653750faac Small bugfixes in freduce pass Clifford Wolf 2013-08-06 15:53:09 +02:00
6efca9ea5a Added freduce command Clifford Wolf 2013-08-06 15:04:52 +02:00
117489f95a Fixed SigPool::del() method Clifford Wolf 2013-08-06 15:04:24 +02:00
ff965424c2 Added proper deallocation of history buffer Clifford Wolf 2013-08-06 15:03:46 +02:00
8b2f7792ba Updated TODO section in README Clifford Wolf 2013-08-01 20:02:15 +02:00
0f38008ed3 Added "design" command (-reset, -save, -load) Clifford Wolf 2013-07-27 14:27:51 +02:00
974b6a947c Added "help -write-web-command-reference-manual" Clifford Wolf 2013-07-26 00:01:31 +02:00
98906b211c Fixed comments in manual rtlil/ilang syntax Clifford Wolf 2013-07-25 15:01:02 +02:00
36c39cbd04 Added RTLIL and Liberty syntax highlighting to manual Clifford Wolf 2013-07-25 14:00:16 +02:00
88d0829d65 Automatically run "proc" on extract map files Clifford Wolf 2013-07-24 20:19:08 +02:00
ad9bbcbf40 Added $lut cells and abc lut mapping support Clifford Wolf 2013-07-23 16:19:34 +02:00
d815f1c770 Fixed "make clean" for manual files Clifford Wolf 2013-07-23 14:19:47 +02:00
3bb1996151 Added web site link to README Clifford Wolf 2013-07-21 15:04:37 +02:00
61ed6b32d1 Added Yosys Manual Clifford Wolf 2013-07-20 15:19:12 +02:00
3650fd7fbe More fixes in ternary op sign handling Clifford Wolf 2013-07-12 13:13:04 +02:00
ded769c98c Fixed sign handling in ternary operator Clifford Wolf 2013-07-12 01:15:37 +02:00
3cd97a205f Added ast frontend refactoring to TODO Clifford Wolf 2013-07-11 19:31:57 +02:00
b380c8c790 Another vloghammer related bugfix Clifford Wolf 2013-07-11 19:24:59 +02:00
a9fefc6ce1 Bugfixes for empty signal vectors Clifford Wolf 2013-07-10 12:52:29 +02:00
ed62fcdbe2 Fixed sign propagation in bit-wise operators Clifford Wolf 2013-07-09 23:53:55 +02:00
5dab327b30 More fixes in ast expression sign/width handling Clifford Wolf 2013-07-09 23:41:28 +02:00
618b2ac994 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-07-09 19:00:10 +02:00
7daeee340a Fixed shift ops with large right hand side Clifford Wolf 2013-07-09 18:59:59 +02:00
00a6c1d9a5 Major redesign of expr width/sign detecion (verilog/ast frontend) Clifford Wolf 2013-07-09 14:31:57 +02:00
e8da3ea7b6 Fixed another bug found using vloghammer Clifford Wolf 2013-07-07 16:49:30 +02:00
eff68560a2 Fixed AST_CONSTANT node generation Clifford Wolf 2013-07-07 15:40:26 +02:00
52d21a63ca Removed tests/xsthammer Clifford Wolf 2013-07-07 13:01:15 +02:00
cf885c4a28 Added opt_clean -purge option Clifford Wolf 2013-07-07 12:59:30 +02:00
0c0197cf45 Fixed handling of $eq and $ne in opt_const Clifford Wolf 2013-07-07 12:59:00 +02:00
92a5961fd3 Fixed vivado related xsthammer bugs Clifford Wolf 2013-07-05 19:33:42 +02:00
940f838dae Various improvements in xsthammer report generator Clifford Wolf 2013-07-05 16:04:02 +02:00
3fd37061bf Added work-around to isim bug in xsthammer report script Clifford Wolf 2013-07-05 15:29:03 +02:00
f519297da9 Fixed gcc warnings in ezminisat Clifford Wolf 2013-07-05 15:00:20 +02:00
238ff14810 Added CARRY4 Xilinx cell to xsthammer cell lib Clifford Wolf 2013-07-05 14:46:33 +02:00
45105faf25 Added xsthammer report generator Clifford Wolf 2013-07-05 14:21:24 +02:00
cd33db25d1 Improved xsthammer quartus support Clifford Wolf 2013-07-04 21:26:49 +02:00
14c84c111b Added Altera Cyclon III cell library to xsthammer Clifford Wolf 2013-07-04 14:50:03 +02:00
a4fd3cde8c Documentation updates Clifford Wolf 2013-07-04 14:17:25 +02:00
56432a920f Added defparam support to Verilog/AST frontend Clifford Wolf 2013-07-04 14:12:33 +02:00
3b294b3912 Added QMAKE makefile variable Clifford Wolf 2013-07-03 23:54:43 +02:00
be1fca3428 Added Altera Quartus support to xsthammer Clifford Wolf 2013-07-03 20:40:54 +02:00
28539541ed Progress in xsthammer Clifford Wolf 2013-07-03 11:19:18 +02:00
a5fe2565b7 Added vivado support to xsthammer Clifford Wolf 2013-06-26 12:34:06 +02:00
101491132f Added SAT support for -all/-max with -verify Clifford Wolf 2013-06-23 13:28:30 +02:00
46b177eb8a Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-06-20 12:49:28 +02:00
8fbb5b6240 Added timout functionality to SAT solver Clifford Wolf 2013-06-20 12:49:10 +02:00
a6aeb3dbf0 Added renaming of wires and cells to "rename" command Clifford Wolf 2013-06-19 16:55:43 +02:00
21e38bed98 Added "eval" pass Clifford Wolf 2013-06-19 09:30:37 +02:00
a046a302f0 Fixed build with clang Clifford Wolf 2013-06-18 19:54:33 +02:00
48aa72ae8f Added splitnets command Clifford Wolf 2013-06-18 17:11:36 +02:00
6971c4db62 Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API Clifford Wolf 2013-06-18 17:11:13 +02:00
5cf04f33fa Added more stuff to xsthammer, found first xst bug Clifford Wolf 2013-06-17 11:30:25 +02:00
c09b66b2a1 Added support for "assign" statements in abc vlparse Clifford Wolf 2013-06-15 13:50:38 +02:00
6ef8c6fb8a Added ternary op and concat op to xsthammer Clifford Wolf 2013-06-15 11:00:34 +02:00
6d7b5f9064 Fixed even more ConstEval bugs found using xsthammer Clifford Wolf 2013-06-14 10:31:18 +02:00
30db70b1ba Added consteval testing to xsthammer and fixed bugs Clifford Wolf 2013-06-13 19:51:13 +02:00
7f6c83a853 More xsthammer improvements (using xst 14.5 now) Clifford Wolf 2013-06-13 17:23:51 +02:00
0c6ffc4c65 More fixes for bugs found using xsthammer Clifford Wolf 2013-06-13 11:18:45 +02:00