yosys

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d60fbaf664 Added EXTRA_TARGETS Makefile variable Clifford Wolf 2013-03-28 16:53:40 +01:00
eff8c68dd9 Improved Makefile: Added ENABLE_* switches Clifford Wolf 2013-03-28 16:50:50 +01:00
73fba5164f Implemented TCL support (only via -c option at the moment) Clifford Wolf 2013-03-28 12:26:17 +01:00
b9870a364e Improved subcircuit verbose output (added portmapper results) Clifford Wolf 2013-03-28 11:36:54 +01:00
c46597b697 Fixed svgviewer hacks for builtin files Clifford Wolf 2013-03-28 10:47:35 +01:00
8edf4f378a Added proper TECHMAP_FAIL support and added support for the celltype attribute in the map file Clifford Wolf 2013-03-28 10:12:50 +01:00
7bfc7b61a8 Implemented proper handling of stub placeholder modules Clifford Wolf 2013-03-28 09:20:10 +01:00
98fcb5daa3 Keep viewport transform stable on reload in yosys-svgviewer Clifford Wolf 2013-03-27 18:48:38 +01:00
92cf7ae2f7 Added check: only one module for "show" unless format is "ps" Clifford Wolf 2013-03-27 18:31:42 +01:00
35a02ee81e Now using SVG and yosys-svgviewer per default in show command Clifford Wolf 2013-03-27 18:14:16 +01:00
9c401b58a2 Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib Clifford Wolf 2013-03-27 10:51:15 +01:00
62b9e16f87 Imported svgviewer from qt4.8 Clifford Wolf 2013-03-27 06:57:57 +01:00
041c06bd9d Create nice errors when calling RTLIL::Module::derive() of base class Clifford Wolf 2013-03-26 19:27:49 +01:00
6a231816fa Collect parameters in hierarchy -generate (and do nothing with them) Clifford Wolf 2013-03-26 19:11:53 +01:00
26f2439551 Tiny bugfix in simlib.v Clifford Wolf 2013-03-26 19:06:28 +01:00
7a99349de4 Improvements and bugfixes for generate blocks with local signals Clifford Wolf 2013-03-26 11:13:58 +01:00
6a382f2aba Fixed handling of unconditional generate blocks Clifford Wolf 2013-03-26 09:44:54 +01:00
227520f94d Added nosync attribute and some async reset related fixes Clifford Wolf 2013-03-25 17:13:14 +01:00
3737964809 Improved verbose output of subcircuit Clifford Wolf 2013-03-25 11:08:52 +01:00
0f5378b559 Improved method for finding fsm_expand candidates Clifford Wolf 2013-03-25 02:24:11 +01:00
4a7d624bef Added hierarchy -generate command for generating skeletton modules Clifford Wolf 2013-03-25 02:14:33 +01:00
4bd6f1ee8e Changed fsm_expand to merge multiplexers more aggressively Clifford Wolf 2013-03-24 17:59:44 +01:00
d9bc024d29 Renamed hansimem.v test case to mem_arst.v Clifford Wolf 2013-03-24 15:25:08 +01:00
e1a80b356e Fixed handling of show -viewer Clifford Wolf 2013-03-24 15:21:57 +01:00
2887e4305f Fixed handling of internal signals in show command Clifford Wolf 2013-03-24 15:15:28 +01:00
181b479e77 Improved show -colors color assignments Clifford Wolf 2013-03-24 13:32:56 +01:00
bbae24bdf7 Added show -strech and renamed -widthlabels to -width Clifford Wolf 2013-03-24 13:27:04 +01:00
f921b06fb0 Added -widthlabels options to chow command Clifford Wolf 2013-03-24 13:11:06 +01:00
05ae20f260 Added -notypes option to intersynth backend Clifford Wolf 2013-03-24 12:05:25 +01:00
8cc1c87ab8 Reorganized TODOs Clifford Wolf 2013-03-24 11:23:54 +01:00
df9753d398 Added mem2reg option to verilog frontend Clifford Wolf 2013-03-24 11:13:32 +01:00
6960df7285 Fixed stdcells.v for $adff with undef reset value Clifford Wolf 2013-03-24 10:43:05 +01:00
3a5244e913 Another fix in mem2reg ast simplify logic Clifford Wolf 2013-03-24 10:42:08 +01:00
55c50dc499 Added -colors option to show command Clifford Wolf 2013-03-24 10:41:24 +01:00
c3c9e5a02f Added hansimem testcase (memory with async reset) Clifford Wolf 2013-03-24 10:40:40 +01:00
bb3357c027 Improved mem2reg handling in ast simplifier Clifford Wolf 2013-03-24 09:27:01 +01:00
a0fa259d81 Fixed gcc build (intersynth backend) Clifford Wolf 2013-03-23 19:01:58 +01:00
e45d1c8865 Tiny fixes to verilog parser Clifford Wolf 2013-03-23 18:54:31 +01:00
bee57c808a Various improvements in intersynth backend Clifford Wolf 2013-03-23 12:02:09 +01:00
80aefb3eaa Added intersynth backend Clifford Wolf 2013-03-23 10:58:14 +01:00
47325fb271 Added help -write-tex-command-reference-manual option Clifford Wolf 2013-03-21 11:33:56 +01:00
69ce1191c0 Added eclipse CDT project files to .gitignore Clifford Wolf 2013-03-21 10:59:35 +01:00
8f610dca58 Added -S option for simple synthesis to gate logic Clifford Wolf 2013-03-21 09:52:21 +01:00
87c7717566 Avoid verilog-2k in verilog backend Clifford Wolf 2013-03-21 09:51:25 +01:00
91b94ef57b Disabled the per-default dumping of ILANG code Clifford Wolf 2013-03-21 09:12:32 +01:00
8d37d1e08b Added -nomap option to memory pass Clifford Wolf 2013-03-21 09:11:06 +01:00
0d39366e2c Merge branch 'hansiglaser-master' Clifford Wolf 2013-03-19 13:47:46 +01:00
9f10acb840 added optimizations for single-bit $eq/$ne with constant input to opt_const Clifford Wolf 2013-03-19 13:33:33 +01:00
d8a7fa6b67 improved $mux optimization in opt_const Clifford Wolf 2013-03-19 13:32:39 +01:00
b7fcf1fb9a keep $mux and $_MUX_ optimizations separate in opt_const Clifford Wolf 2013-03-19 13:32:04 +01:00
1d30c66a7f added a TODO Johann Glaser 2013-03-18 22:06:53 +01:00
69674652c5 added one more suggestion to optimize MUXes in pass "opt_const" Johann Glaser 2013-03-18 22:06:16 +01:00
a4e2c887f1 also optimize single-bit "$mux" cells in pass "opt_const", added suggestions for more optimizations Johann Glaser 2013-03-18 22:05:21 +01:00
15ad2db8fc fixed a crash when lines start with whitespace Johann Glaser 2013-03-18 20:58:47 +01:00
2192873daa added description of Makefile include files for build configuration Johann Glaser 2013-03-18 19:26:35 +01:00
71de666003 More TODOs in README Clifford Wolf 2013-03-18 15:05:15 +01:00
bc5489f7ec Merge branch 'hansi' Clifford Wolf 2013-03-18 07:33:53 +01:00
020a35d11e Removed date from auto-generated passes/techmap/stdcells.inc Clifford Wolf 2013-03-18 07:32:33 +01:00
52914c2e68 Fixed abc eeror handling Clifford Wolf 2013-03-18 07:31:59 +01:00
3b8ebd694d add header to autogenerated file on its origin Johann Glaser 2013-03-17 22:02:46 +01:00
cd8008bda0 fixed typos Johann Glaser 2013-03-17 22:02:30 +01:00
ba3793b642 Fixed strerrno vs. strerror types in ABC pass Clifford Wolf 2013-03-17 09:28:58 +01:00
0133a98b73 Merge branch 'hansi' Clifford Wolf 2013-03-17 09:18:00 +01:00
1390de4b74 Cleaned up ABC file/io error handling Clifford Wolf 2013-03-17 09:17:18 +01:00
e6cbeb5b16 Set execute bit on tests/openmsp430/run-synth.sh for real Clifford Wolf 2013-03-17 09:10:09 +01:00
0cb4a5936f added error checking at execution of ABC Johann Glaser 2013-03-16 22:04:55 +01:00
fb494d4dd7 corrected typos Johann Glaser 2013-03-16 21:29:45 +01:00
a6f004e6f8 set executable flags to run-synth.sh, added .gitignore Johann Glaser 2013-03-16 21:23:25 +01:00
3cfbc18601 added ckeck for Icarus Verilog, otherwise the tests are silently stopped Johann Glaser 2013-03-16 21:21:38 +01:00
bcae4aae6e corrected typos Johann Glaser 2013-03-16 21:20:38 +01:00
35b4a2c553 Fixed gcc warnings and added error handling to shell escape Clifford Wolf 2013-03-15 10:29:25 +01:00
cd5767d61b Added scc pass (find logic loops) Clifford Wolf 2013-03-15 10:24:08 +01:00
13b2279b6c Added vi .*.swp files to .gitignore Clifford Wolf 2013-03-15 10:23:53 +01:00
10956cb84a Added [[CITE]] tags to abc and fsm_extract passes Clifford Wolf 2013-03-15 10:23:02 +01:00
89f009d171 Added additional functionality and cleanups in sigtools.h and celltypes.h Clifford Wolf 2013-03-15 10:22:23 +01:00
3377a04bf2 Changed prefix for selection operators from # to % Clifford Wolf 2013-03-14 16:15:24 +01:00
697cf1eb80 Added #ci and #co selection operators Clifford Wolf 2013-03-14 15:57:47 +01:00
b35add5f8c Added more features to #x selection operator Clifford Wolf 2013-03-14 15:35:05 +01:00
b0f386751c Added "select -write" command Clifford Wolf 2013-03-14 13:02:10 +01:00
11789db206 More support code for $sr cells Clifford Wolf 2013-03-14 11:15:00 +01:00
de823ce964 Added $sr cell type to celltypes.h Clifford Wolf 2013-03-14 01:08:30 +01:00
55f927eecb Fixed detection of public wires in opt_rmunused Clifford Wolf 2013-03-10 14:20:03 +01:00
eadf73c823 Added shell escape to command language Clifford Wolf 2013-03-10 14:05:42 +01:00
0be19f6ca7 Fixed and improved #x selection operator Clifford Wolf 2013-03-08 10:15:15 +01:00
b96ffed69b Automatically select new objects in abc and techmap passes Clifford Wolf 2013-03-08 09:16:25 +01:00
79b3afa011 Added ## selection operator (union all on stack) Clifford Wolf 2013-03-08 08:47:29 +01:00
653f0049a8 Added select -count mode Clifford Wolf 2013-03-08 08:31:12 +01:00
ef4f1c55b6 Split extract -attr into extract -cell_attr and -wire_attr Clifford Wolf 2013-03-08 08:19:24 +01:00
bf3a3b9589 Added support for attribute matching in extract pass Clifford Wolf 2013-03-07 18:51:17 +01:00
ed1ddea83b Added portmapping support to subcircuit userCompareNodes() api Clifford Wolf 2013-03-07 17:54:18 +01:00
b070b82187 Cleanups and improvements in Makefile Clifford Wolf 2013-03-07 17:34:40 +01:00
8960bba9b5 Fixed parsing of select #x<num> operator Clifford Wolf 2013-03-06 19:01:08 +01:00
f2f3e2cb19 Improved error message on failed module load Clifford Wolf 2013-03-06 18:30:45 +01:00
b380af9d6d Added support for loadable modules (aka plugins) Clifford Wolf 2013-03-06 11:58:07 +01:00
14c097b633 Reset Makefile default config setting (oops) Clifford Wolf 2013-03-06 09:46:21 +01:00
9f2c7d0936 Fixed mine test case for subcircuit library Clifford Wolf 2013-03-06 09:44:29 +01:00
594dbc4c93 Fixed handling of constant values and port swapping in subcircuit library Clifford Wolf 2013-03-06 09:38:47 +01:00
4347423ca6 Changed default value for extract -mine_cells_span Clifford Wolf 2013-03-05 21:52:57 +01:00
21696c8367 Added some simple progress information to verbose subcircuit miner output Clifford Wolf 2013-03-05 19:22:59 +01:00
29c17fddf5 Implemented -mine_split option to extract pass Clifford Wolf 2013-03-05 13:50:31 +01:00