14 lines
215 B
Verilog
14 lines
215 B
Verilog
// Demo for assertpmux
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module demo6 (input A, B, C, D, E, output reg Y);
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always @* begin
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Y = 0;
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if (A != B) begin
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(* parallel_case *)
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case (C)
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A: Y = D;
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B: Y = E;
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endcase
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end
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end
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endmodule
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