516 lines
18 KiB
TeX
516 lines
18 KiB
TeX
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\section{Yosys by example -- Synthesis}
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\begin{frame}
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\sectionpage
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Typical Phases of a Synthesis Flow}
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\begin{frame}{\subsecname}
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\begin{itemize}
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\item Reading and elaborating the design
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\item Higher-level synthesis and optimization
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\begin{itemize}
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\item Converting {\tt always}-blocks to logic and registers
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\item Perform coarse-grain optimizations (resource sharing, const folding, ...)
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\item Handling of memories and other coarse-grain blocks
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\item Extracting and optimizing finite state machines
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\end{itemize}
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\item Convert remaining logic to bit-level logic functions
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\item Perform optimizations on bit-level logic functions
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\item Map bit-level logic gates and registers to cell library
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\item Write results to output file
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\end{itemize}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Reading the design}
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\begin{frame}[fragile]{\subsecname}
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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read_verilog file1.v
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read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v
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read_verilog -lib cell_library.v
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verilog_defaults -add -I include_dir
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read_verilog file3.v
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read_verilog file4.v
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verilog_defaults -clear
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verilog_defaults -push
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verilog_defaults -add -I include_dir
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read_verilog file5.v
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read_verilog file6.v
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verilog_defaults -pop
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\end{lstlisting}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Design elaboration}
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\begin{frame}[fragile]{\subsecname}
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During design elaboration Yosys figures out how the modules are hierarchically
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connected. It also re-runs the AST parts of the Verilog frontend to create
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all needed variations of parametric modules.
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\bigskip
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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# simplest form. at least this version should be used after reading all input files
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#
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hierarchy
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# recommended form. fails if parts of the design hierarchy are missing, removes
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# everything that is unreachable from the top module, and marks the top module.
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#
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hierarchy -check -top top_module
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\end{lstlisting}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{The {\tt proc} command}
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\begin{frame}[fragile]{\subsecname}
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The Verilog frontend converts {\tt always}-blocks to RTL netlists for the
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expressions and ``processes'' for the control- and memory elements.
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\medskip
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The {\tt proc} command transforms this ``processes'' to netlists of RTL
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multiplexer and register cells.
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\medskip
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The {\tt proc} command is actually a macro-command that calls the following
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other commands:
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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proc_clean # remove empty branches and processes
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proc_rmdead # remove unreachable branches
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proc_init # special handling of "initial" blocks
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proc_arst # identify modeling of async resets
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proc_mux # convert decision trees to multiplexer networks
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proc_dff # extract registers from processes
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proc_clean # if all went fine, this should remove all the processes
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\end{lstlisting}
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\medskip
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Many commands can not operate on modules with ``processes'' in them. Usually
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a call to {\tt proc} is the first command in the actual synthesis procedure
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after design elaboration.
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\end{frame}
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\begin{frame}[fragile]{\subsecname{} -- Example 1/3}
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_01.v}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/proc_01.ys}
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\end{columns}
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\hfil\includegraphics[width=8cm,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_01.pdf}
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\end{frame}
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\begin{frame}[t, fragile]{\subsecname{} -- Example 2/3}
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\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2.5cm]{PRESENTATION_ExSyn/proc_02.pdf}\vss}
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\vskip-1cm
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_02.v}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/proc_02.ys}
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\end{columns}
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\end{frame}
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\begin{frame}[t, fragile]{\subsecname{} -- Example 3/3}
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\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -1.5cm]{PRESENTATION_ExSyn/proc_03.pdf}\vss}
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\vskip-1cm
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/proc_03.ys}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_03.v}
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\end{columns}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{The {\tt opt} command}
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\begin{frame}[fragile]{\subsecname}
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The {\tt opt} command implements a series of simple optimizations. It also
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is a macro command that calls other commands:
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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opt_expr # const folding and simple expression rewriting
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opt_merge -nomux # merging identical cells
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do
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opt_muxtree # remove never-active branches from multiplexer tree
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opt_reduce # consolidate trees of boolean ops to reduce functions
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opt_merge # merging identical cells
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opt_rmdff # remove/simplify registers with constant inputs
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opt_clean # remove unused objects (cells, wires) from design
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opt_expr # const folding and simple expression rewriting
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while [changed design]
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\end{lstlisting}
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The command {\tt clean} can be used as alias for {\tt opt\_clean}. And {\tt ;;}
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can be used as shortcut for {\tt clean}. For example:
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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proc; opt; memory; opt_expr;; fsm;;
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\end{lstlisting}
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\end{frame}
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\begin{frame}[t, fragile]{\subsecname{} -- Example 1/4}
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\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -0.5cm]{PRESENTATION_ExSyn/opt_01.pdf}\vss}
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\vskip-1cm
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_01.ys}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_01.v}
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\end{columns}
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\end{frame}
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\begin{frame}[t, fragile]{\subsecname{} -- Example 2/4}
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\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm 0cm]{PRESENTATION_ExSyn/opt_02.pdf}\vss}
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\vskip-1cm
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_02.ys}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_02.v}
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\end{columns}
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\end{frame}
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\begin{frame}[t, fragile]{\subsecname{} -- Example 3/4}
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\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2cm]{PRESENTATION_ExSyn/opt_03.pdf}\vss}
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\vskip-1cm
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_03.ys}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_03.v}
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\end{columns}
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\end{frame}
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\begin{frame}[t, fragile]{\subsecname{} -- Example 4/4}
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\vbox to 0cm{\hskip6cm\includegraphics[width=6cm,trim=0cm 0cm 0cm -3cm]{PRESENTATION_ExSyn/opt_04.pdf}\vss}
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\vskip-1cm
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/opt_04.v}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/opt_04.ys}
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\end{columns}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{When to use {\tt opt} or {\tt clean}}
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\begin{frame}{\subsecname}
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Usually it does not hurt to call {\tt opt} after each regular command in the
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synthesis script. But it increases the synthesis time, so it is favourable
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to only call {\tt opt} when an improvement can be achieved.
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\bigskip
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The designs in {\tt yosys-bigsim} are a good playground for experimenting with
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the effects of calling {\tt opt} in various places of the flow.
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\bigskip
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It generally is a good idea to call {\tt opt} before inherently expensive
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commands such as {\tt sat} or {\tt freduce}, as the possible gain is much
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higher in this cases as the possible loss.
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\bigskip
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The {\tt clean} command on the other hand is very fast and many commands leave
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a mess (dangling signal wires, etc). For example, most commands do not remove
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any wires or cells. They just change the connections and depend on a later
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call to clean to get rid of the now unused objects. So the occasional {\tt ;;}
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is a good idea in every synthesis script.
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{The {\tt memory} command}
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\begin{frame}[fragile]{\subsecname}
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In the RTL netlist, memory reads and writes are individual cells. This makes
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consolidating the number of ports for a memory easier. The {\tt memory}
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transforms memories to an implementation. Per default that is logic for address
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decoders and registers. It also is a macro command that calls other commands:
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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# this merges registers into the memory read- and write cells.
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memory_dff
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# this collects all read and write cells for a memory and transforms them
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# into one multi-port memory cell.
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memory_collect
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# this takes the multi-port memory cell and transforms it to address decoder
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# logic and registers. This step is skipped if "memory" is called with -nomap.
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memory_map
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\end{lstlisting}
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\bigskip
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Usually it is preferred to use architecture-specific RAM resources for memory.
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For example:
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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memory -nomap; techmap -map my_memory_map.v; memory_map
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\end{lstlisting}
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\end{frame}
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\begin{frame}[t, fragile]{\subsecname{} -- Example 1/2}
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\vbox to 0cm{\includegraphics[width=0.7\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
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\vskip-1cm
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/memory_01.ys}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_01.v}
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\end{columns}
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\end{frame}
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\begin{frame}[t, fragile]{\subsecname{} -- Example 2/2}
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\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -5cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
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\vskip-1cm
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/memory_02.v}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/memory_02.ys}
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\end{columns}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{The {\tt fsm} command}
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\begin{frame}[fragile]{\subsecname{}}
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The {\tt fsm} command identifies, extracts, optimizes (re-encodes), and
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re-synthesizes finite state machines. It again is a macro that calls
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a series of other commands:
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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fsm_detect # unless got option -nodetect
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fsm_extract
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fsm_opt
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clean
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fsm_opt
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fsm_expand # if got option -expand
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clean # if got option -expand
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fsm_opt # if got option -expand
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fsm_recode # unless got option -norecode
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fsm_info
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fsm_export # if got option -export
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fsm_map # unless got option -nomap
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\end{lstlisting}
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\end{frame}
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\begin{frame}{\subsecname{} -- details}
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Some details on the most important commands from the {\tt fsm\_*} group:
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\bigskip
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The {\tt fsm\_detect} command identifies FSM state registers and marks them
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with the {\tt (* fsm\_encoding = "auto" *)} attribute, if they do not have the
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{\tt fsm\_encoding} set already. Mark registers with {\tt (* fsm\_encoding =
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"none" *)} to disable FSM optimization for a register.
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\bigskip
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The {\tt fsm\_extract} command replaces the entire FSM (logic and state
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registers) with a {\tt \$fsm} cell.
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\bigskip
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The commands {\tt fsm\_opt} and {\tt fsm\_recode} can be used to optimize the
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FSM.
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\bigskip
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Finally the {\tt fsm\_map} command can be used to convert the (optimized) {\tt
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\$fsm} cell back to logic and registers.
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{The {\tt techmap} command}
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\begin{frame}[t]{\subsecname}
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\vbox to 0cm{\includegraphics[width=12cm,trim=-15cm 0cm 0cm -20cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss}
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\vskip-0.8cm
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The {\tt techmap} command replaces cells with implementations given as
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verilog source. For example implementing a 32 bit adder using 16 bit adders:
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\vbox to 0cm{
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\vskip-0.3cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/techmap_01_map.v}
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}\vbox to 0cm{
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\vskip-0.5cm
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\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExSyn/techmap_01.v}
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\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/techmap_01.ys}
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}
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\end{frame}
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\begin{frame}[t]{\subsecname{} -- stdcell mapping}
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When {\tt techmap} is used without a map file, it uses a built-in map file
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to map all RTL cell types to a generic library of built-in logic gates and registers.
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\bigskip
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\begin{block}{The built-in logic gate types are:}
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{\tt \$\_NOT\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
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\end{block}
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\bigskip
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\begin{block}{The register types are:}
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{\tt \$\_SR\_NN\_ \$\_SR\_NP\_ \$\_SR\_PN\_ \$\_SR\_PP\_ \\
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\$\_DFF\_N\_ \$\_DFF\_P\_ \\
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\$\_DFF\_NN0\_ \$\_DFF\_NN1\_ \$\_DFF\_NP0\_ \$\_DFF\_NP1\_ \\
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\$\_DFF\_PN0\_ \$\_DFF\_PN1\_ \$\_DFF\_PP0\_ \$\_DFF\_PP1\_ \\
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\$\_DFFSR\_NNN\_ \$\_DFFSR\_NNP\_ \$\_DFFSR\_NPN\_ \$\_DFFSR\_NPP\_ \\
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\$\_DFFSR\_PNN\_ \$\_DFFSR\_PNP\_ \$\_DFFSR\_PPN\_ \$\_DFFSR\_PPP\_ \\
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\$\_DLATCH\_N\_ \$\_DLATCH\_P\_}
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\end{block}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{The {\tt abc} command}
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\begin{frame}{\subsecname}
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The {\tt abc} command provides an interface to ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}},
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an open source tool for low-level logic synthesis.
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\medskip
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The {\tt abc} command processes a netlist of internal gate types and can perform:
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\begin{itemize}
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\item logic minimization (optimization)
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\item mapping of logic to standard cell library (liberty format)
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\item mapping of logic to k-LUTs (for FPGA synthesis)
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\end{itemize}
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\medskip
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Optionally {\tt abc} can process registers from one clock domain and perform
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sequential optimization (such as register balancing).
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\medskip
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ABC is also controlled using scripts. An ABC script can be specified to use
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more advanced ABC features. It is also possible to write the design with
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{\tt write\_blif} and load the output file into ABC outside of Yosys.
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\end{frame}
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\begin{frame}[fragile]{\subsecname{} -- Example}
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\begin{columns}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/abc_01.v}
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\column[t]{5cm}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/abc_01.ys}
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\end{columns}
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\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/abc_01.pdf}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Other special-purpose mapping commands}
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\begin{frame}{\subsecname}
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\begin{block}{\tt dfflibmap}
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This command maps the internal register cell types to the register types
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described in a liberty file.
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\end{block}
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\bigskip
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\begin{block}{\tt hilomap}
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Some architectures require special driver cells for driving a constant hi or lo
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value. This command replaces simple constants with instances of such driver cells.
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\end{block}
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\bigskip
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\begin{block}{\tt iopadmap}
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Top-level input/outputs must usually be implemented using special I/O-pad cells.
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This command inserts this cells to the design.
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\end{block}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Example Synthesis Script}
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\begin{frame}[fragile]{\subsecname}
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\begin{columns}
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\column[t]{4cm}
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=ys]
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# read and elaborate design
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read_verilog cpu_top.v cpu_ctrl.v cpu_regs.v
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read_verilog -D WITH_MULT cpu_alu.v
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hierarchy -check -top cpu_top
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# high-level synthesis
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proc; opt; fsm;; memory -nomap; opt
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# substitute block rams
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techmap -map map_rams.v
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# map remaining memories
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|
memory_map
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# low-level synthesis
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techmap; opt; flatten;; abc -lut6
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|
techmap -map map_xl_cells.v
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# add clock buffers
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select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d
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iopadmap -inpad BUFGP O:I @xl_clocks
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|
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# add io buffers
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select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d
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iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks
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|
|
|
# write synthesis results
|
|
write_edif synth.edif
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|
\end{lstlisting}
|
|
\column[t]{6cm}
|
|
\vskip1cm
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|
\begin{block}{Teaser / Outlook}
|
|
\small\parbox{6cm}{
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The weird {\tt select} expressions at the end of this script are discussed in
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|
the next part (Section 3, ``Advanced Synthesis'') of this presentation.}
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|
\end{block}
|
|
\end{columns}
|
|
\end{frame}
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
|
\subsection{Summary}
|
|
|
|
\begin{frame}{\subsecname}
|
|
\begin{itemize}
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|
\item Yosys provides commands for each phase of the synthesis.
|
|
\item Each command solves a (more or less) simple problem.
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|
\item Complex commands are often only front-ends to simple commands.
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|
\item {\tt proc; opt; fsm; opt; memory; opt; techmap; opt; abc;;}
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\end{itemize}
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|
\bigskip
|
|
\bigskip
|
|
\begin{center}
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|
Questions?
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|
\end{center}
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|
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|
\bigskip
|
|
\bigskip
|
|
\begin{center}
|
|
\url{http://www.clifford.at/yosys/}
|
|
\end{center}
|
|
\end{frame}
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