This website requires JavaScript.
Explore
Help
Sign In
stv0g
/
yosys
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Pull Requests
Releases
Wiki
Activity
master
yosys
/
manual
/
PRESENTATION_Prog
/
absval_ref.v
4 lines
97 B
Verilog
Raw
Permalink
Blame
History
module
absval_ref
(
input
signed
[
3
:
0
]
a
,
output
[
3
:
0
]
y
)
;
assign
y
=
a
[
3
]
?
-
a
:
a
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink