yosys/tests/asicworld/code_tidbits_nonblocking.v
2013-01-05 11:13:26 +01:00

17 lines
165 B
Verilog

module nonblocking (clk,a,c);
input clk;
input a;
output c;
wire clk;
wire a;
reg c;
reg b;
always @ (posedge clk )
begin
b <= a;
c <= b;
end
endmodule