yosys/tests/asicworld/code_verilog_tutorial_good_code.v
2013-01-05 11:13:26 +01:00

18 lines
345 B
Verilog

module addbit (
a,
b,
ci,
sum,
co);
input a;
input b;
input ci;
output sum;
output co;
wire a;
wire b;
wire ci;
wire sum;
wire co;
endmodule