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091d9abc3e
yosys
/
frontends
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verilog
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Clifford Wolf
6170cfe9cd
Added verilog_defaults command
2014-01-17 17:22:29 +01:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
const2ast.cc
Major redesign of expr width/sign detecion (verilog/ast frontend)
2013-07-09 14:31:57 +02:00
lexer.l
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
Makefile.inc
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
parser.y
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
preproc.cc
Fixed parsing of non-arg macro calls followed by "("
2013-12-27 16:25:27 +01:00
verilog_frontend.cc
Added verilog_defaults command
2014-01-17 17:22:29 +01:00
verilog_frontend.h
Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
2013-11-22 12:46:02 +01:00