This website requires JavaScript.
Explore
Help
Sign in
stv0g
/
yosys
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Pull requests
Releases
Wiki
Activity
0d7fd2585e
yosys
/
techlibs
History
Clifford Wolf
a75f94ec4a
Run dffsr2dff in synth_xilinx
2016-02-13 08:20:19 +01:00
..
common
Progress in cell library documentation
2016-02-01 13:58:10 +01:00
greenpak4
Added nlutmap
2015-09-18 21:57:34 +02:00
ice40
Work around DDR dout sim glitches in ice40 SB_IO sim model
2016-02-07 11:19:48 +01:00
xilinx
Run dffsr2dff in synth_xilinx
2016-02-13 08:20:19 +01:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00