Clifford Wolf 274bcef66c Improved detection of primary wire for a signal in opt_clean		2014-02-07 23:50:17 +01:00
..
abc	Re-enabled abc "retime" after sorting yout the yosys-bigsim problem	2014-02-07 16:36:37 +01:00
cmds	Added splice command	2014-02-07 20:30:56 +01:00
extract	enabled multiple "-map" for the extract pass	2014-01-25 21:11:34 +01:00
fsm	Fixes in fsm detect/extract for better detection of non-fsm circuits	2013-12-06 12:53:20 +01:00
hierarchy	Added hierarchy -purge_lib option	2014-02-04 16:50:13 +01:00
memory	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
opt	Improved detection of primary wire for a signal in opt_clean	2014-02-07 23:50:17 +01:00
proc	Tiny cleanup in proc_mux.cc	2014-01-03 16:54:59 +01:00
sat	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	2014-02-06 19:22:46 +01:00
scc	fixed typos	2013-03-18 07:28:31 +01:00
submod	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
techmap	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00