Andrew Zonenberg 2b062c48cb greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)		2016-08-13 22:27:58 -07:00
..
cells_map.v	Added tri-state I/O extraction for GreenPak	2016-05-03 22:53:29 -07:00
cells_sim.v	greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)	2016-08-13 22:27:58 -07:00
gp_dff.lib	Fixed indenting in techlibs/greenpak4/gp_dff.lib	2016-03-29 13:44:14 +02:00
greenpak4_counters.cc	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Makefile.inc	Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract	2016-05-04 15:55:16 -07:00
synth_greenpak4.cc	synth_greenpak4: use attrmvcp to move LOC from wires to cells.	2016-08-10 20:09:35 +00:00