yosys/tests/sat/asserts.ys
Clifford Wolf 482d9208aa Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
2014-06-12 11:54:20 +02:00

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read_verilog -sv asserts.v
hierarchy; proc; opt
sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts