10 lines
196 B
Verilog
10 lines
196 B
Verilog
module test #( parameter v2kparam = 5)
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(in, out, io, vin, vout, vio);
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input in;
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output out;
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inout io;
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input [3:0] vin;
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output [v2kparam:0] vout;
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inout [0:3] vio;
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parameter myparam = 10;
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endmodule
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